[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Michael Maitland via llvm-commits]

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@@ -14,3 +14,15 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
 
 /// Floating Point Registers: F.
 def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Register Banks:
+def VRRegBank : RegisterBank<"VRB", [VR]>;
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michaelmaitland wrote:

> RISCVInstructionSelector::getRegClassForTypeOnBank is responsible for converting from RegBank+LLT to register class.

It looks like its going from RegClass + LLT -> RegBank. I guess I am confused what the register banks are useful for? 

> The register allocator doesn't know about register banks.

Are you sure this is the case? The docs say `Register Banks are a means to constrain the register allocator...`.

https://github.com/llvm/llvm-project/pull/71541