[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[Craig Topper via llvm-commits]

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@@ -14,3 +14,15 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
 
 /// Floating Point Registers: F.
 def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Register Banks:
+def VRRegBank : RegisterBank<"VRB", [VR]>;
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topperc wrote:

Note that description for Register Banks says "particular register file". The vector registers make up a single register file thus should be a single register bank.

> My aim was that we'd constrain the register allocator to only use register that work for M2.

The register allocator doesn't know about register banks. It only knows about register classes. `RISCVInstructionSelector::getRegClassForTypeOnBank` is responsible for converting from RegBank+LLT to register class. LMUL is encoded in the scalable vector type so you should be able to pick the correct LMUL register class from a single bank.

> On a separate, but related note, do you think should VR and VM registers have different banks?

Single register bank.

https://github.com/llvm/llvm-project/pull/71541