[llvm] [Mips] In LowerShift*Parts, xor with bits-1 instead of -1. (PR #71149)

[via llvm-commits]

yingopq wrote:

> There's another bug in this code that neither patch addresses.
> 
> I believe this violates the boolean rules. ISD::SELECT should only receive 0/1 as a condition. There needs to be a setcc here.
> 
> ```
>   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,                      
>                              DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 
>   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,                                    
>                    DAG.getConstant(0, DL, VT), ShiftLeftLo); 
> ```

There has a question about shift number 129, now we deal with it as shift number 1 and the result of `shl i128 %a, %b` was `ffffffffffffffff fffffffffffffffe`.
If we add a setcc like the following diff, the above result was `fffffffffffffffe 0000000000000000` like RISCV `RISCVTargetLowering::lowerShiftLeftParts`.  Whether we're going to change the behavior of the shift number 129?
```diff
+//  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
+//                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
+
+  SDValue MinusXLen = DAG.getConstant(-(int)VT.getSizeInBits(), DL, MVT::i32);
+  SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, MVT::i32, Shamt, MinusXLen);
+  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
+  SDValue CC = DAG.getSetCC(DL, MVT::i32, ShamtMinusXLen, Zero, ISD::SETLT);
+  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, ShiftLeftLo, DAG.getConstant(0, DL, VT));
+  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, Or, ShiftLeftLo);

```


https://github.com/llvm/llvm-project/pull/71149