[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 7 12:28:40 PST 2023
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/71541
>From e9d762c7ae8bca9eeba59d57973a46ef49dbb3cc Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 7 Nov 2023 06:25:02 -0800
Subject: [PATCH 1/2] [RISCV] Use TypeSize in places where needed for
RegBankSelection
---
llvm/include/llvm/CodeGen/RegisterBankInfo.h | 4 ++--
llvm/lib/CodeGen/MachineVerifier.cpp | 4 ++--
llvm/lib/CodeGen/RegisterBankInfo.cpp | 9 +++++----
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/RegisterBankInfo.h
index 1ee1f6b6c32ed63..b353ea8b3cc86ec 100644
--- a/llvm/include/llvm/CodeGen/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterBankInfo.h
@@ -177,7 +177,7 @@ class RegisterBankInfo {
/// \note This method does not check anything when assertions are disabled.
///
/// \return True is the check was successful.
- bool verify(const RegisterBankInfo &RBI, unsigned MeaningfulBitWidth) const;
+ bool verify(const RegisterBankInfo &RBI, TypeSize MeaningfulBitWidth) const;
/// Print this on dbgs() stream.
void dump() const;
@@ -749,7 +749,7 @@ class RegisterBankInfo {
/// virtual register.
///
/// \pre \p Reg != 0 (NoRegister).
- unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
+ TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const;
/// Check that information hold by this instance make sense for the
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index dc15f0d3b842304..8f2c42bfac88229 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2256,8 +2256,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
// Make sure the register fits into its register bank if any.
- if (RegBank && Ty.isValid() &&
- RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
+ if (RegBank && Ty.isValid() && (!Ty.isScalable() &&
+ RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits())) {
report("Register bank is too small for virtual register", MO,
MONum);
errs() << "Register bank " << RegBank->getName() << " too small("
diff --git a/llvm/lib/CodeGen/RegisterBankInfo.cpp b/llvm/lib/CodeGen/RegisterBankInfo.cpp
index f9721d7d9386958..6a96bb40f56aed9 100644
--- a/llvm/lib/CodeGen/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterBankInfo.cpp
@@ -495,7 +495,7 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
}
}
-unsigned RegisterBankInfo::getSizeInBits(Register Reg,
+TypeSize RegisterBankInfo::getSizeInBits(Register Reg,
const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const {
if (Reg.isPhysical()) {
@@ -553,7 +553,7 @@ bool RegisterBankInfo::ValueMapping::partsAllUniform() const {
}
bool RegisterBankInfo::ValueMapping::verify(const RegisterBankInfo &RBI,
- unsigned MeaningfulBitWidth) const {
+ TypeSize MeaningfulBitWidth) const {
assert(NumBreakDowns && "Value mapped nowhere?!");
unsigned OrigValueBitWidth = 0;
for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
@@ -565,8 +565,9 @@ bool RegisterBankInfo::ValueMapping::verify(const RegisterBankInfo &RBI,
OrigValueBitWidth =
std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
}
- assert(OrigValueBitWidth >= MeaningfulBitWidth &&
- "Meaningful bits not covered by the mapping");
+ assert(MeaningfulBitWidth.isScalable() ||
+ OrigValueBitWidth >= MeaningfulBitWidth &&
+ "Meaningful bits not covered by the mapping");
APInt ValueMask(OrigValueBitWidth, 0);
for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
// Check that the union of the partial mappings covers the whole value,
>From db2a757d0f32bc17303258816725bf2dd794b866 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 7 Nov 2023 06:25:13 -0800
Subject: [PATCH 2/2] [RISCV][GISEL] Add vector RegisterBanks and vector
support in getRegBankFromRegClass
Vector Register banks are created for the various register vector
register groupings. getRegBankFromRegClass is implemented to go from
vector TargetRegisterClass to the corresponding vector RegisterBank.
---
llvm/lib/CodeGen/MachineVerifier.cpp | 4 +-
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 20 +
.../Target/RISCV/GISel/RISCVRegisterBanks.td | 12 +
.../GlobalISel/regbankselect/vec-args.mir | 1058 +++++++++++++++++
4 files changed, 1092 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args.mir
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 8f2c42bfac88229..b6dcfc0a741a3de 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2256,8 +2256,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
// Make sure the register fits into its register bank if any.
- if (RegBank && Ty.isValid() && (!Ty.isScalable() &&
- RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits())) {
+ if (RegBank && Ty.isValid() && !(Ty.isVector() && Ty.isScalable()) &&
+ RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
report("Register bank is too small for virtual register", MO,
MONum);
errs() << "Register bank " << RegBank->getName() << " too small("
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 02b89b902b9924f..a045c02ccc77a78 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -100,6 +100,26 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
case RISCV::FPR64CRegClassID:
case RISCV::FPR32CRegClassID:
return getRegBank(RISCV::FPRRegBankID);
+ case RISCV::VRRegClassID:
+ return getRegBank(RISCV::VRRegBankID);
+ case RISCV::VRNoV0RegClassID:
+ return getRegBank(RISCV::VRNoV0RegBankID);
+ case RISCV::VRM2RegClassID:
+ return getRegBank(RISCV::VRM2RegBankID);
+ case RISCV::VRM2NoV0RegClassID:
+ return getRegBank(RISCV::VRM2NoV0RegBankID);
+ case RISCV::VRM4RegClassID:
+ return getRegBank(RISCV::VRM4RegBankID);
+ case RISCV::VRM4NoV0RegClassID:
+ return getRegBank(RISCV::VRM4NoV0RegBankID);
+ case RISCV::VRM8RegClassID:
+ return getRegBank(RISCV::VRM8RegBankID);
+ case RISCV::VRM8NoV0RegClassID:
+ return getRegBank(RISCV::VRM8NoV0RegBankID);
+ case RISCV::VMRegClassID:
+ return getRegBank(RISCV::VMRegBankID);
+ case RISCV::VMV0RegClassID:
+ return getRegBank(RISCV::VMV0RegBankID);
}
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
index 49f18e19c2269fd..40ef98d2badde1d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
@@ -14,3 +14,15 @@ def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
/// Floating Point Registers: F.
def FPRRegBank : RegisterBank<"FPRB", [FPR64]>;
+
+/// Vector Register Banks:
+def VRRegBank : RegisterBank<"VRB", [VR]>;
+def VRNoV0RegBank : RegisterBank<"VRNoV0B", [VRNoV0]>;
+def VRM2RegBank : RegisterBank<"VRM2B", [VRM2]>;
+def VRM2NoV0RegBank : RegisterBank<"VRM2NoV0B", [VRM2NoV0]>;
+def VRM4RegBank : RegisterBank<"VRM4B", [VRM4]>;
+def VRM4NoV0RegBank : RegisterBank<"VRM4NoV0B", [VRM4NoV0]>;
+def VRM8RegBank : RegisterBank<"VRM8B", [VRM8]>;
+def VRM8NoV0RegBank : RegisterBank<"VRM8NoV0B", [VRM8NoV0]>;
+def VMRegBank : RegisterBank<"VMB", [VM]>;
+def VMV0RegBank : RegisterBank<"VMNoV0B", [VMV0]>;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args.mir
new file mode 100644
index 000000000000000..340db97f3fe01c7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args.mir
@@ -0,0 +1,1058 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefixes=RV32 %s
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
+# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck -check-prefixes=RV64 %s
+
+---
+name: test_args_nxv1i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1i8
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i8
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s8>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv2i8
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i8
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s8>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv4i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv4i8
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i8
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s8>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv8i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv8i8
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 8 x s8>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i8
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 8 x s8>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s8>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv16i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv16i8
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i8
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 16 x s8>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 16 x s8>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv32i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv32i8
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 32 x s8>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32i8
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 32 x s8>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 32 x s8>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv64i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv64i8
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 64 x s8>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv64i8
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 64 x s8>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 64 x s8>) = COPY $v8m8
+ PseudoRET
+...
+---
+name: test_args_nxv1i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1i16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv2i16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv4i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv4i16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv8i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv8i16
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i16
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s16>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv16i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv16i16
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i16
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 16 x s16>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv32i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv32i16
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32i16
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 32 x s16>) = COPY $v8m8
+ PseudoRET
+...
+---
+name: test_args_nxv1i32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1i32
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i32
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s32>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2i32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv2i32
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i32
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s32>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv4i32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv4i32
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i32
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s32>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv8i32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv8i32
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i32
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s32>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv16i32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv16i32
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i32
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 16 x s32>) = COPY $v8m8
+ PseudoRET
+...
+---
+name: test_args_nxv1i64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1i64
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s64>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i64
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s64>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s64>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2i64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv2i64
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i64
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s64>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv4i64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv4i64
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i64
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s64>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv8i64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv8i64
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i64
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s64>) = COPY $v8m8
+ PseudoRET
+...
+---
+name: test_args_nxv64i1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv64i1
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 64 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv64i1
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 64 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 64 x s1>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv32i1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv32i1
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 32 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32i1
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 32 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 32 x s1>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv16i1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv16i1
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 16 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16i1
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 16 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 16 x s1>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv8i1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv8i1
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 8 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8i1
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 8 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s1>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv4i1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv4i1
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4i1
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s1>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2i1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv2i1
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2i1
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s1>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv1i1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1i1
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s1>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1i1
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s1>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s1>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv1f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1f32
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1f32
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s32>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv2f32
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s32>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2f32
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s32>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s32>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv4f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv4f32
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4f32
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 4 x s32>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s32>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv8f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv8f32
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8f32
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 8 x s32>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s32>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv16f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv16f32
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16f32
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 16 x s32>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 16 x s32>) = COPY $v8m8
+ PseudoRET
+...
+---
+name: test_args_nxv1f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1f64
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s64>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1f64
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s64>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s64>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv2f64
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2f64
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 2 x s64>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s64>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv4f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv4f64
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4f64
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 4 x s64>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s64>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv8f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv8f64
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8f64
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 8 x s64>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s64>) = COPY $v8m8
+ PseudoRET
+...
+---
+name: test_args_nxv1f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1f16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1f16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv2f16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2f16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv4f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv4f16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4f16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv8f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv8f16
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8f16
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s16>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv16f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv16f16
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16f16
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 16 x s16>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv32f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv32f16
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32f16
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 32 x s16>) = COPY $v8m8
+ PseudoRET
+...
+---
+name: test_args_nxv1b16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv1b16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv1b16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 1 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 1 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv2b16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv2b16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv2b16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 2 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 2 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv4b16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8
+ ; RV32-LABEL: name: test_args_nxv4b16
+ ; RV32: liveins: $v8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s16>) = COPY $v8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv4b16
+ ; RV64: liveins: $v8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrnov0b(<vscale x 4 x s16>) = COPY $v8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 4 x s16>) = COPY $v8
+ PseudoRET
+...
+---
+name: test_args_nxv8b16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m2
+ ; RV32-LABEL: name: test_args_nxv8b16
+ ; RV32: liveins: $v8m2
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv8b16
+ ; RV64: liveins: $v8m2
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm2nov0b(<vscale x 8 x s16>) = COPY $v8m2
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 8 x s16>) = COPY $v8m2
+ PseudoRET
+...
+---
+name: test_args_nxv16b16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m4
+ ; RV32-LABEL: name: test_args_nxv16b16
+ ; RV32: liveins: $v8m4
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv16b16
+ ; RV64: liveins: $v8m4
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm4nov0b(<vscale x 16 x s16>) = COPY $v8m4
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 16 x s16>) = COPY $v8m4
+ PseudoRET
+...
+---
+name: test_args_nxv32b16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $v8m8
+ ; RV32-LABEL: name: test_args_nxv32b16
+ ; RV32: liveins: $v8m8
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV32-NEXT: PseudoRET
+ ;
+ ; RV64-LABEL: name: test_args_nxv32b16
+ ; RV64: liveins: $v8m8
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: [[COPY:%[0-9]+]]:vrm8nov0b(<vscale x 32 x s16>) = COPY $v8m8
+ ; RV64-NEXT: PseudoRET
+ %0:_(<vscale x 32 x s16>) = COPY $v8m8
+ PseudoRET
+...
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