[llvm] [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass (PR #71541)

[via llvm-commits]

github-actions[bot] wrote:

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``````````bash
git-clang-format --diff 5db63d29fdc1fbf301c3d010d6e00e004d82fcdc 74adabca1a5bc51d174134f2def25102544daf68 -- llvm/include/llvm/CodeGen/RegisterBankInfo.h llvm/include/llvm/CodeGen/TargetRegisterInfo.h llvm/lib/CodeGen/MachineVerifier.cpp llvm/lib/CodeGen/RegisterBankInfo.cpp llvm/lib/CodeGen/TargetRegisterInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 8f2c42bfac88..38a6ac3602ee 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2256,8 +2256,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
           }
 
           // Make sure the register fits into its register bank if any.
-          if (RegBank && Ty.isValid() && (!Ty.isScalable() &&
-              RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits())) {
+          if (RegBank && Ty.isValid() &&
+              (!Ty.isScalable() &&
+               RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits())) {
             report("Register bank is too small for virtual register", MO,
                    MONum);
             errs() << "Register bank " << RegBank->getName() << " too small("

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https://github.com/llvm/llvm-project/pull/71541