[llvm] [AMDGPU] Move WWM register pre-allocation to during regalloc (PR #70618)

[Carl Ritson via llvm-commits]

perlfu wrote:

> Change looks good overall but I don't quite understand this:
> 
> > I realized that we need to explicitly ignore SI_SPILL_S32_TO_VGPR instructions which occur in STRICT_WWM sections otherwise they will unintentionally be assigned WWM registers. This brings the total test diff on this down massive to primarily wwm-reserved-spill.ll, which shows a change in use of registers because SGPR spill now get first access to VGPRs before WWM pre-allocation runs.
> 
> Do SI_SPILL_S32_TO_VGPR instructions refer to _physical_ VGPRs? If so, why do you need to explicitly ignore them in this pass?
> 
> If SI_SPILL_S32_TO_VGPR instructions refer to virtual VGPRs then I don't understand how they "get first access to [physical?] VGPRs".

SI_SPILL_S32_TO_VGPR can take a physical or virtual VGPR.
The decision to use a physical register is made during SGPR spill lowering based on whether the function is an entry function or not.
In the entry function, physical VGPRs will be assigned for VGPR spill registers.

So a high level we currently have two independent code paths which can allocate physical registers for WWM use.
Unifying them is beyond the scope of this change, but is a near term objective which could be built on this patch.

https://github.com/llvm/llvm-project/pull/70618