[llvm] LegalizeVectorTypes: fix bug in widening of vec result in xrint (PR #71198)

[Ramkumar Ramachandra via llvm-commits]

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@@ -101,6 +134,21 @@ define <4 x iXLen> @lrint_v4f32(<4 x float> %x) {
 ; X86-AVX-NEXT:    vcvtss2si %xmm0, %eax
 ; X86-AVX-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
 ; X86-AVX-NEXT:    retl
+;
+; X64-AVX-i32-LABEL: lrint_v4f32:
+; X64-AVX-i32:       # %bb.0:
+; X64-AVX-i32-NEXT:    vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; X64-AVX-i32-NEXT:    vcvtss2si %xmm1, %eax
+; X64-AVX-i32-NEXT:    vcvtss2si %xmm0, %ecx
+; X64-AVX-i32-NEXT:    vmovd %ecx, %xmm1
+; X64-AVX-i32-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
+; X64-AVX-i32-NEXT:    vshufpd {{.*#+}} xmm2 = xmm0[1,0]
+; X64-AVX-i32-NEXT:    vcvtss2si %xmm2, %eax
+; X64-AVX-i32-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
+; X64-AVX-i32-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; X64-AVX-i32-NEXT:    vcvtss2si %xmm0, %eax
+; X64-AVX-i32-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
+; X64-AVX-i32-NEXT:    retq
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artagnon wrote:

I noticed this too, but update_llc_test_checks.py doesn't seem to generate them. I'll check if I introduced a regression in UTC.

https://github.com/llvm/llvm-project/pull/71198