[llvm] [CodeGen][MachineVerifier] Use TypeSize instead of unsigned for getRe… (PR #70881)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

> Do you plan to mark register sizes as scalable?

I hadn't really thought much into that idea. I posted a patch for call lowering here: https://github.com/llvm/llvm-project/pull/70882. I hadn't come across the need to mark the register sizes as scalable. I think what I had in mind is that scalable vectors map to some fixed size LMUL and SEW grouping on RISCV because of that, we'd lower into those types and not have to think much harder about scalable vectors. 

What did you have in mind? Do you see a need to mark the reg sizes as scalable?

> I was looking at the bare minimum needed to get scalable vectors working for GlobalISel last week, and got something that worked, but would likely hit a lot of other problems. I wasn't sure if it would end up being necessary to mark the registers as scalable, the patch I had was still very much work-in-progress.

If you have a patch/patches I am more than happy to review. If you want to have a chat about what scalable vectors in GISel will/should look like, we can set up a call.

https://github.com/llvm/llvm-project/pull/70881