[llvm] [RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (PR #70357)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

Thanks for testing! I must missed something when I tried this.

I see from the diff that we can remove some complexities of GISel. My concern is that we add too much complexities to DAG lowering and TableGen patterns and I don't know if it's worthy.

https://github.com/llvm/llvm-project/pull/70357