[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Michael Maitland via llvm-commits]

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@@ -427,7 +535,8 @@ void RISCVPassConfig::addPreRegAlloc() {
   addPass(createRISCVPreRAExpandPseudoPass());
   if (TM->getOptLevel() != CodeGenOptLevel::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
-  addPass(createRISCVInsertVSETVLIPass());
+  if (!EnableSplitRA)
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michaelmaitland wrote:

IIUC, there is nothing stopping us from being able to do split register allocation with the vsetvli insertion pass remaining where it was.

I think we should have an option for enabling split register allocation, and another option for enabling late vsetvli insertion. That way we can have the following functionality:

1. Split register allocation && early vsetvli insertion 
2. Split register allocation && late vsetvli insertion
3. Non-split register allocation && early vsetvli insertion
4. Non-split register allocation && late vsetvli insertion

This flexibility may allow us to pinpoint exactly where the shortcomings are (do they come from split regalloc, late vsetvli insertion, or the combination of both)?

https://github.com/llvm/llvm-project/pull/70549