[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Roger Ferrer Ibáñez via llvm-commits]

rofirrim wrote:

Oh, very interesting! Thanks for working on this. I didn't know we could do partial register allocation (RA)!

I have some high-level questions:

> 1. unblock scheduler's constraints by removing vl/vtype def-use chain

Just for me to understand, this would not require RA of RVV registers byt itself. We would still need to run the InsertVSETVL pass late, like you're doing now. Is that correct?

However splitting the passes unlocks the two following cases:

>  2. Support RVV re-materialization

I understand that here you will we able to do that because you have only RA'd RVV registers and the GPR virtual registers that we use as carriers of the VL value make this a bit easier. Is my intuition correct here?

> 3. Support partial spill

Similar as above, I imagine you plan to emit a `PseudoVSPILL_VL` / `PseudoVRELOAD_VL` instruction or something like that, right?

Did you consider partial copies as well?

I * think * some of those might be hindered by the tail undisturbed policy which may still require to spill/copy the whole register. Do you think it does or it would already be handled after RA of RVV registers?

Looking forward progress here, this looks promising!

https://github.com/llvm/llvm-project/pull/70549