[llvm] c92c86f - [RISCV] Add test coverage for "zext nneg" [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 30 13:48:40 PDT 2023
That's the way I'd read it. I just copied the existing zext coverage
without a lot of thought to whether the configuration was useful.
This should be probably be combined in instcombine, but support for this
IR feature just landed today, so we're missing a bunch of "obvious"
transforms.
Philip
On 10/30/23 13:46, Craig Topper wrote:
> The test cases extending from i1, mean the i1 is 0 I think in order
> for it to be non-negative?
>
>
> ~Craig
>
>
> On Mon, Oct 30, 2023 at 1:36 PM Philip Reames via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
>
>
> Author: Philip Reames
> Date: 2023-10-30T13:35:58-07:00
> New Revision: c92c86f66a72c2a07dce4976ab26446e5f272875
>
> URL:
> https://github.com/llvm/llvm-project/commit/c92c86f66a72c2a07dce4976ab26446e5f272875
> DIFF:
> https://github.com/llvm/llvm-project/commit/c92c86f66a72c2a07dce4976ab26446e5f272875.diff
>
> LOG: [RISCV] Add test coverage for "zext nneg" [nfc]
>
> This IR feature was recently added in #67982. An upcoming change will
> improve our lowering on these examples.
>
> Added:
>
>
> Modified:
> llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
>
> Removed:
>
>
>
> ################################################################################
> diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
> b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
> index 98488c9a589a3a8..7297bfaf0c62ec7 100644
> --- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
> +++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
> @@ -350,6 +350,164 @@ define i64 @zext_i32_to_i64(i32 %a) nounwind {
> ret i64 %1
> }
>
> +define i8 @zext_nneg_i1_to_i8(i1 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i1_to_i8:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: andi a0, a0, 1
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i1_to_i8:
> +; RV64: # %bb.0:
> +; RV64-NEXT: andi a0, a0, 1
> +; RV64-NEXT: ret
> + %1 = zext nneg i1 %a to i8
> + ret i8 %1
> +}
> +
> +define i16 @zext_nneg_i1_to_i16(i1 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i1_to_i16:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: andi a0, a0, 1
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i1_to_i16:
> +; RV64: # %bb.0:
> +; RV64-NEXT: andi a0, a0, 1
> +; RV64-NEXT: ret
> + %1 = zext nneg i1 %a to i16
> + ret i16 %1
> +}
> +
> +define i32 @zext_nneg_i1_to_i32(i1 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i1_to_i32:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: andi a0, a0, 1
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i1_to_i32:
> +; RV64: # %bb.0:
> +; RV64-NEXT: andi a0, a0, 1
> +; RV64-NEXT: ret
> + %1 = zext nneg i1 %a to i32
> + ret i32 %1
> +}
> +
> +define i64 @zext_nneg_i1_to_i64(i1 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i1_to_i64:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: andi a0, a0, 1
> +; RV32I-NEXT: li a1, 0
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i1_to_i64:
> +; RV64: # %bb.0:
> +; RV64-NEXT: andi a0, a0, 1
> +; RV64-NEXT: ret
> + %1 = zext nneg i1 %a to i64
> + ret i64 %1
> +}
> +
> +define i16 @zext_nneg_i8_to_i16(i8 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i8_to_i16:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: andi a0, a0, 255
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i8_to_i16:
> +; RV64: # %bb.0:
> +; RV64-NEXT: andi a0, a0, 255
> +; RV64-NEXT: ret
> + %1 = zext nneg i8 %a to i16
> + ret i16 %1
> +}
> +
> +define i32 @zext_nneg_i8_to_i32(i8 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i8_to_i32:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: andi a0, a0, 255
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i8_to_i32:
> +; RV64: # %bb.0:
> +; RV64-NEXT: andi a0, a0, 255
> +; RV64-NEXT: ret
> + %1 = zext nneg i8 %a to i32
> + ret i32 %1
> +}
> +
> +define i64 @zext_nneg_i8_to_i64(i8 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i8_to_i64:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: andi a0, a0, 255
> +; RV32I-NEXT: li a1, 0
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i8_to_i64:
> +; RV64: # %bb.0:
> +; RV64-NEXT: andi a0, a0, 255
> +; RV64-NEXT: ret
> + %1 = zext nneg i8 %a to i64
> + ret i64 %1
> +}
> +
> +define i32 @zext_nneg_i16_to_i32(i16 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i16_to_i32:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: slli a0, a0, 16
> +; RV32I-NEXT: srli a0, a0, 16
> +; RV32I-NEXT: ret
> +;
> +; RV64I-LABEL: zext_nneg_i16_to_i32:
> +; RV64I: # %bb.0:
> +; RV64I-NEXT: slli a0, a0, 48
> +; RV64I-NEXT: srli a0, a0, 48
> +; RV64I-NEXT: ret
> +;
> +; RV64ZBB-LABEL: zext_nneg_i16_to_i32:
> +; RV64ZBB: # %bb.0:
> +; RV64ZBB-NEXT: zext.h a0, a0
> +; RV64ZBB-NEXT: ret
> + %1 = zext nneg i16 %a to i32
> + ret i32 %1
> +}
> +
> +define i64 @zext_nneg_i16_to_i64(i16 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i16_to_i64:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: slli a0, a0, 16
> +; RV32I-NEXT: srli a0, a0, 16
> +; RV32I-NEXT: li a1, 0
> +; RV32I-NEXT: ret
> +;
> +; RV64I-LABEL: zext_nneg_i16_to_i64:
> +; RV64I: # %bb.0:
> +; RV64I-NEXT: slli a0, a0, 48
> +; RV64I-NEXT: srli a0, a0, 48
> +; RV64I-NEXT: ret
> +;
> +; RV64ZBB-LABEL: zext_nneg_i16_to_i64:
> +; RV64ZBB: # %bb.0:
> +; RV64ZBB-NEXT: zext.h a0, a0
> +; RV64ZBB-NEXT: ret
> + %1 = zext nneg i16 %a to i64
> + ret i64 %1
> +}
> +
> +define i64 @zext_nneg_i32_to_i64(i32 %a) nounwind {
> +; RV32I-LABEL: zext_nneg_i32_to_i64:
> +; RV32I: # %bb.0:
> +; RV32I-NEXT: li a1, 0
> +; RV32I-NEXT: ret
> +;
> +; RV64-LABEL: zext_nneg_i32_to_i64:
> +; RV64: # %bb.0:
> +; RV64-NEXT: slli a0, a0, 32
> +; RV64-NEXT: srli a0, a0, 32
> +; RV64-NEXT: ret
> + %1 = zext nneg i32 %a to i64
> + ret i64 %1
> +}
> +
> define i1 @trunc_i8_to_i1(i8 %a) nounwind {
> ; RV32I-LABEL: trunc_i8_to_i1:
> ; RV32I: # %bb.0:
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20231030/d0f25f34/attachment.html>
More information about the llvm-commits
mailing list