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<p>That's the way I'd read it. I just copied the existing zext
coverage without a lot of thought to whether the configuration was
useful.</p>
<p>This should be probably be combined in instcombine, but support
for this IR feature just landed today, so we're missing a bunch of
"obvious" transforms.</p>
<p>Philip<br>
</p>
<div class="moz-cite-prefix">On 10/30/23 13:46, Craig Topper wrote:<br>
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<blockquote type="cite"
cite="mid:CAF7ks-MascfOkXf6Sm+136wSGMD=uTt12rFyVJxBJDQxOXisMw@mail.gmail.com">
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<div>The test cases extending from i1, mean the i1 is 0 I think
in order for it to be non-negative?</div>
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<div dir="ltr" class="gmail_signature"
data-smartmail="gmail_signature">~Craig</div>
</div>
<br>
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<br>
<div class="gmail_quote">
<div dir="ltr" class="gmail_attr">On Mon, Oct 30, 2023 at
1:36 PM Philip Reames via llvm-commits <<a
href="mailto:llvm-commits@lists.llvm.org"
moz-do-not-send="true" class="moz-txt-link-freetext">llvm-commits@lists.llvm.org</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote"
style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Philip Reames<br>
Date: 2023-10-30T13:35:58-07:00<br>
New Revision: c92c86f66a72c2a07dce4976ab26446e5f272875<br>
<br>
URL: <a
href="https://github.com/llvm/llvm-project/commit/c92c86f66a72c2a07dce4976ab26446e5f272875"
rel="noreferrer" target="_blank" moz-do-not-send="true"
class="moz-txt-link-freetext">https://github.com/llvm/llvm-project/commit/c92c86f66a72c2a07dce4976ab26446e5f272875</a><br>
DIFF: <a
href="https://github.com/llvm/llvm-project/commit/c92c86f66a72c2a07dce4976ab26446e5f272875.diff"
rel="noreferrer" target="_blank" moz-do-not-send="true"
class="moz-txt-link-freetext">https://github.com/llvm/llvm-project/commit/c92c86f66a72c2a07dce4976ab26446e5f272875.diff</a><br>
<br>
LOG: [RISCV] Add test coverage for "zext nneg" [nfc]<br>
<br>
This IR feature was recently added in #67982. An upcoming
change will<br>
improve our lowering on these examples.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll<br>
index 98488c9a589a3a8..7297bfaf0c62ec7 100644<br>
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll<br>
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll<br>
@@ -350,6 +350,164 @@ define i64 @zext_i32_to_i64(i32 %a)
nounwind {<br>
ret i64 %1<br>
}<br>
<br>
+define i8 @zext_nneg_i1_to_i8(i1 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i1_to_i8:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: andi a0, a0, 1<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i1_to_i8:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: andi a0, a0, 1<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i1 %a to i8<br>
+ ret i8 %1<br>
+}<br>
+<br>
+define i16 @zext_nneg_i1_to_i16(i1 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i1_to_i16:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: andi a0, a0, 1<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i1_to_i16:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: andi a0, a0, 1<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i1 %a to i16<br>
+ ret i16 %1<br>
+}<br>
+<br>
+define i32 @zext_nneg_i1_to_i32(i1 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i1_to_i32:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: andi a0, a0, 1<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i1_to_i32:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: andi a0, a0, 1<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i1 %a to i32<br>
+ ret i32 %1<br>
+}<br>
+<br>
+define i64 @zext_nneg_i1_to_i64(i1 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i1_to_i64:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: andi a0, a0, 1<br>
+; RV32I-NEXT: li a1, 0<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i1_to_i64:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: andi a0, a0, 1<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i1 %a to i64<br>
+ ret i64 %1<br>
+}<br>
+<br>
+define i16 @zext_nneg_i8_to_i16(i8 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i8_to_i16:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: andi a0, a0, 255<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i8_to_i16:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: andi a0, a0, 255<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i8 %a to i16<br>
+ ret i16 %1<br>
+}<br>
+<br>
+define i32 @zext_nneg_i8_to_i32(i8 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i8_to_i32:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: andi a0, a0, 255<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i8_to_i32:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: andi a0, a0, 255<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i8 %a to i32<br>
+ ret i32 %1<br>
+}<br>
+<br>
+define i64 @zext_nneg_i8_to_i64(i8 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i8_to_i64:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: andi a0, a0, 255<br>
+; RV32I-NEXT: li a1, 0<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i8_to_i64:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: andi a0, a0, 255<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i8 %a to i64<br>
+ ret i64 %1<br>
+}<br>
+<br>
+define i32 @zext_nneg_i16_to_i32(i16 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i16_to_i32:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: slli a0, a0, 16<br>
+; RV32I-NEXT: srli a0, a0, 16<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64I-LABEL: zext_nneg_i16_to_i32:<br>
+; RV64I: # %bb.0:<br>
+; RV64I-NEXT: slli a0, a0, 48<br>
+; RV64I-NEXT: srli a0, a0, 48<br>
+; RV64I-NEXT: ret<br>
+;<br>
+; RV64ZBB-LABEL: zext_nneg_i16_to_i32:<br>
+; RV64ZBB: # %bb.0:<br>
+; RV64ZBB-NEXT: zext.h a0, a0<br>
+; RV64ZBB-NEXT: ret<br>
+ %1 = zext nneg i16 %a to i32<br>
+ ret i32 %1<br>
+}<br>
+<br>
+define i64 @zext_nneg_i16_to_i64(i16 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i16_to_i64:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: slli a0, a0, 16<br>
+; RV32I-NEXT: srli a0, a0, 16<br>
+; RV32I-NEXT: li a1, 0<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64I-LABEL: zext_nneg_i16_to_i64:<br>
+; RV64I: # %bb.0:<br>
+; RV64I-NEXT: slli a0, a0, 48<br>
+; RV64I-NEXT: srli a0, a0, 48<br>
+; RV64I-NEXT: ret<br>
+;<br>
+; RV64ZBB-LABEL: zext_nneg_i16_to_i64:<br>
+; RV64ZBB: # %bb.0:<br>
+; RV64ZBB-NEXT: zext.h a0, a0<br>
+; RV64ZBB-NEXT: ret<br>
+ %1 = zext nneg i16 %a to i64<br>
+ ret i64 %1<br>
+}<br>
+<br>
+define i64 @zext_nneg_i32_to_i64(i32 %a) nounwind {<br>
+; RV32I-LABEL: zext_nneg_i32_to_i64:<br>
+; RV32I: # %bb.0:<br>
+; RV32I-NEXT: li a1, 0<br>
+; RV32I-NEXT: ret<br>
+;<br>
+; RV64-LABEL: zext_nneg_i32_to_i64:<br>
+; RV64: # %bb.0:<br>
+; RV64-NEXT: slli a0, a0, 32<br>
+; RV64-NEXT: srli a0, a0, 32<br>
+; RV64-NEXT: ret<br>
+ %1 = zext nneg i32 %a to i64<br>
+ ret i64 %1<br>
+}<br>
+<br>
define i1 @trunc_i8_to_i1(i8 %a) nounwind {<br>
; RV32I-LABEL: trunc_i8_to_i1:<br>
; RV32I: # %bb.0:<br>
<br>
<br>
<br>
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