[llvm] [RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (PR #70266)

[Wang Pengcheng via llvm-commits]

================
@@ -62,6 +62,44 @@ multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
     def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
 }
 
+// Define a SchedAlias for the SchedWrite associated with (name, mx) whose
+// behavior is aliased to a Variant. The Variant has Latency predLad and
+// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has
+// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite
+// is created similiarly if IsWorstCase is true.
+multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
+                                 list<ProcResourceKind> resources,
+                                 int predLat, list<int> predCycles,
+                                 int noPredLat, list<int> noPredCycles,
+                                 string mx, bit IsWorstCase> {
+  defvar nameMX = name # "_" # mx;
+
+  // Define the different behaviors
+  def NAME # nameMX # "_Pred" : SchedWriteRes<resources>
+  { let Latency = predLat; let ReleaseAtCycles = predCycles; }
+  def NAME # nameMX # "_NoPred" : SchedWriteRes<resources>
+  { let Latency = noPredLat; let ReleaseAtCycles = noPredCycles; }
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wangpc-pp wrote:

```suggestion
  def NAME # nameMX # "_Pred" : SchedWriteRes<resources> {
    let Latency = predLat;
    let ReleaseAtCycles = predCycles;
  }
  def NAME # nameMX # "_NoPred" : SchedWriteRes<resources> {
    let Latency = noPredLat;
    let ReleaseAtCycles = noPredCycles;
  }
```
The format here is not matched with others I think.

https://github.com/llvm/llvm-project/pull/70266