[llvm] 2228b35 - Revert "Revert "[InstCombine] Add oneuse checks to shr + cmp constant folds.""
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 28 03:12:23 PDT 2023
Author: Amara Emerson
Date: 2023-10-28T03:12:15-07:00
New Revision: 2228b35f93256449ca2524ed38dd068b87163efc
URL: https://github.com/llvm/llvm-project/commit/2228b35f93256449ca2524ed38dd068b87163efc
DIFF: https://github.com/llvm/llvm-project/commit/2228b35f93256449ca2524ed38dd068b87163efc.diff
LOG: Revert "Revert "[InstCombine] Add oneuse checks to shr + cmp constant folds.""
This reverts commit d37b283cdd37feca5ea71456cf350005add268e7.
There was a simple logic bug in the else path. Tests codegen is different with
the fix.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/test/Transforms/InstCombine/ashr-icmp-minmax-idiom-break.ll
llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll
llvm/test/Transforms/InstCombine/icmp-shr.ll
llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index d254c4706e0aacd..1764917107f03f4 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -2451,7 +2451,7 @@ Instruction *InstCombinerImpl::foldICmpShrConstant(ICmpInst &Cmp,
// constant-value-based preconditions in the folds below, then we could assert
// those conditions rather than checking them. This is
diff icult because of
// undef/poison (PR34838).
- if (IsAShr) {
+ if (IsAShr && Shr->hasOneUse()) {
if (IsExact || Pred == CmpInst::ICMP_SLT || Pred == CmpInst::ICMP_ULT) {
// When ShAmtC can be shifted losslessly:
// icmp PRED (ashr exact X, ShAmtC), C --> icmp PRED X, (C << ShAmtC)
@@ -2491,7 +2491,7 @@ Instruction *InstCombinerImpl::foldICmpShrConstant(ICmpInst &Cmp,
ConstantInt::getAllOnesValue(ShrTy));
}
}
- } else {
+ } else if (!IsAShr) {
if (Pred == CmpInst::ICMP_ULT || (Pred == CmpInst::ICMP_UGT && IsExact)) {
// icmp ult (lshr X, ShAmtC), C --> icmp ult X, (C << ShAmtC)
// icmp ugt (lshr exact X, ShAmtC), C --> icmp ugt X, (C << ShAmtC)
diff --git a/llvm/test/Transforms/InstCombine/ashr-icmp-minmax-idiom-break.ll b/llvm/test/Transforms/InstCombine/ashr-icmp-minmax-idiom-break.ll
index a539b9136689682..c6d6e916b2c7867 100644
--- a/llvm/test/Transforms/InstCombine/ashr-icmp-minmax-idiom-break.ll
+++ b/llvm/test/Transforms/InstCombine/ashr-icmp-minmax-idiom-break.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
-; This test is pre-committed to show sub-optimal codegen due to
-; min/max idiom breakage. On AArch64, these constants are also expensive to materialize,
+; Check we don't have sub-optimal codegen due to min/max idiom breakage.
+; On AArch64, these constants are also expensive to materialize,
; and therefore generate poor code vs maintaining the min/max idiom.
define i64 @dont_break_minmax_i64(i64 %conv, i64 %conv2) {
@@ -10,8 +10,7 @@ define i64 @dont_break_minmax_i64(i64 %conv, i64 %conv2) {
; CHECK-SAME: (i64 [[CONV:%.*]], i64 [[CONV2:%.*]]) {
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV2]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[MUL]], 4
-; CHECK-NEXT: [[CMP4_I:%.*]] = icmp slt i64 [[MUL]], 5579712
-; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = select i1 [[CMP4_I]], i64 [[SHR]], i64 348731
+; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = call i64 @llvm.smin.i64(i64 [[SHR]], i64 348731)
; CHECK-NEXT: ret i64 [[SPEC_SELECT_I]]
;
%mul = mul nsw i64 %conv, %conv2
diff --git a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll
index 08a763a50bf958d..1b8efe4351c6dcc 100644
--- a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll
@@ -900,7 +900,7 @@ define i1 @ashrsgt_01_00(i4 %x) {
define i1 @ashrsgt_01_00_multiuse(i4 %x, ptr %p) {
; CHECK-LABEL: @ashrsgt_01_00_multiuse(
; CHECK-NEXT: [[S:%.*]] = ashr i4 [[X:%.*]], 1
-; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[X]], 1
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], 0
; CHECK-NEXT: store i4 [[S]], ptr [[P:%.*]], align 1
; CHECK-NEXT: ret i1 [[C]]
;
@@ -2442,7 +2442,7 @@ define i1 @ashr_sle_noexact(i8 %x) {
define i1 @ashr_00_00_ashr_extra_use(i8 %x, ptr %ptr) {
; CHECK-LABEL: @ashr_00_00_ashr_extra_use(
; CHECK-NEXT: [[S:%.*]] = ashr exact i8 [[X:%.*]], 3
-; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X]], 88
+; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[S]], 11
; CHECK-NEXT: store i8 [[S]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: ret i1 [[C]]
;
diff --git a/llvm/test/Transforms/InstCombine/icmp-shr.ll b/llvm/test/Transforms/InstCombine/icmp-shr.ll
index 253b38c8bfe596f..44beb5c1c578b19 100644
--- a/llvm/test/Transforms/InstCombine/icmp-shr.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-shr.ll
@@ -780,7 +780,7 @@ define i1 @ashr_ult_2(i4 %x) {
define i1 @ashr_ult_2_multiuse(i4 %x, ptr %p) {
; CHECK-LABEL: @ashr_ult_2_multiuse(
; CHECK-NEXT: [[S:%.*]] = ashr i4 [[X:%.*]], 1
-; CHECK-NEXT: [[R:%.*]] = icmp ult i4 [[X]], 4
+; CHECK-NEXT: [[R:%.*]] = icmp ult i4 [[S]], 2
; CHECK-NEXT: store i4 [[S]], ptr [[P:%.*]], align 1
; CHECK-NEXT: ret i1 [[R]]
;
diff --git a/llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll b/llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll
index 8559f973f281ace..67d721b23d6f008 100644
--- a/llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll
+++ b/llvm/test/Transforms/PhaseOrdering/icmp-ashr-breaking-select-idiom.ll
@@ -5,8 +5,7 @@ define i32 @testa(i32 %mul) {
; CHECK-LABEL: define i32 @testa(
; CHECK-SAME: i32 [[MUL:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[MUL]], 15
-; CHECK-NEXT: [[CMP4_I:%.*]] = icmp slt i32 [[MUL]], 1073741824
-; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = select i1 [[CMP4_I]], i32 [[SHR]], i32 32767
+; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = tail call i32 @llvm.smin.i32(i32 [[SHR]], i32 32767)
; CHECK-NEXT: ret i32 [[SPEC_SELECT_I]]
;
%shr = ashr i32 %mul, 15
@@ -20,11 +19,8 @@ define i32 @testb(i32 %mul) {
; CHECK-LABEL: define i32 @testb(
; CHECK-SAME: i32 [[MUL:%.*]]) local_unnamed_addr #[[ATTR0]] {
; CHECK-NEXT: [[SHR102:%.*]] = ashr i32 [[MUL]], 7
-; CHECK-NEXT: [[CMP4_I:%.*]] = icmp sgt i32 [[MUL]], 16383
-; CHECK-NEXT: [[RETVAL_0_I:%.*]] = select i1 [[CMP4_I]], i32 127, i32 -128
-; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[MUL]], 16384
-; CHECK-NEXT: [[CLEANUP_DEST_SLOT_0_I:%.*]] = icmp ult i32 [[TMP1]], 32768
-; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = select i1 [[CLEANUP_DEST_SLOT_0_I]], i32 [[SHR102]], i32 [[RETVAL_0_I]]
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.smax.i32(i32 [[SHR102]], i32 -128)
+; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = tail call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127)
; CHECK-NEXT: ret i32 [[SPEC_SELECT_I]]
;
%shr102 = ashr i32 %mul, 7
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