[llvm] [RISCV] Add `TuneVentanaVeyron` subtarget feature. (PR #70414)

[Craig Topper via llvm-commits]

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@@ -46,11 +46,13 @@ struct RISCVTuneInfo {
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
 public:
+  // clang-format off
   enum RISCVProcFamilyEnum : uint8_t {
     Others,
     SiFive7,
+    VentanaVeyron
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topperc wrote:

Leave a trailing comma after this. Makes it easier to insert new CPUs without touching this line.

https://github.com/llvm/llvm-project/pull/70414