[llvm] b679ec8 - [RISCV] Use RISCVInstrInfo::movImm to implement most of RISCVPostRAExpandPseudo::expandMovImm (#70389)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 27 13:36:07 PDT 2023
Author: Craig Topper
Date: 2023-10-27T13:35:56-07:00
New Revision: b679ec86e3cba95b1858077fb78bfff46080eb73
URL: https://github.com/llvm/llvm-project/commit/b679ec86e3cba95b1858077fb78bfff46080eb73
DIFF: https://github.com/llvm/llvm-project/commit/b679ec86e3cba95b1858077fb78bfff46080eb73.diff
LOG: [RISCV] Use RISCVInstrInfo::movImm to implement most of RISCVPostRAExpandPseudo::expandMovImm (#70389)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d430524bb11e1f4..fdc9c08ef9343ac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -776,7 +776,8 @@ MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, Register DstReg, uint64_t Val,
- MachineInstr::MIFlag Flag) const {
+ MachineInstr::MIFlag Flag, bool DstRenamable,
+ bool DstIsDead) const {
Register SrcReg = RISCV::X0;
if (!STI.is64Bit() && !isInt<32>(Val))
@@ -786,28 +787,39 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
RISCVMatInt::generateInstSeq(Val, STI.getFeatureBits());
assert(!Seq.empty());
+ bool SrcRenamable = false;
+ unsigned Num = 0;
+
for (const RISCVMatInt::Inst &Inst : Seq) {
- unsigned SrcRegState = getKillRegState(SrcReg != RISCV::X0);
+ bool LastItem = ++Num == Seq.size();
+ unsigned DstRegState = getDeadRegState(DstIsDead && LastItem) |
+ getRenamableRegState(DstRenamable);
+ unsigned SrcRegState = getKillRegState(SrcReg != RISCV::X0) |
+ getRenamableRegState(SrcRenamable);
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
- BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
+ .addReg(DstReg, RegState::Define | DstRegState)
.addImm(Inst.getImm())
.setMIFlag(Flag);
break;
case RISCVMatInt::RegX0:
- BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
+ .addReg(DstReg, RegState::Define | DstRegState)
.addReg(SrcReg, SrcRegState)
.addReg(RISCV::X0)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegReg:
- BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
+ .addReg(DstReg, RegState::Define | DstRegState)
.addReg(SrcReg, SrcRegState)
.addReg(SrcReg, SrcRegState)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegImm:
- BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
+ .addReg(DstReg, RegState::Define | DstRegState)
.addReg(SrcReg, SrcRegState)
.addImm(Inst.getImm())
.setMIFlag(Flag);
@@ -816,6 +828,7 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
// Only the first instruction has X0 as its source.
SrcReg = DstReg;
+ SrcRenamable = DstRenamable;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 13f1bd4127b12b7..0777c5abac012e5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -97,7 +97,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
// Materializes the given integer Val into DstReg.
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, Register DstReg, uint64_t Val,
- MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
+ MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
+ bool DstRenamable = false, bool DstIsDead = false) const;
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
index 2a5b693a5b4f59d..bc9b66d6ca6b114 100644
--- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
@@ -92,48 +92,13 @@ bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
Val, MBB.getParent()->getSubtarget().getFeatureBits());
assert(!Seq.empty());
- Register SrcReg = RISCV::X0;
Register DstReg = MBBI->getOperand(0).getReg();
bool DstIsDead = MBBI->getOperand(0).isDead();
bool Renamable = MBBI->getOperand(0).isRenamable();
- bool SrcRenamable = false;
- unsigned Num = 0;
-
- for (RISCVMatInt::Inst &Inst : Seq) {
- bool LastItem = ++Num == Seq.size();
- unsigned DstRegState = getDeadRegState(DstIsDead && LastItem) |
- getRenamableRegState(Renamable);
- unsigned SrcRegState = getKillRegState(SrcReg != RISCV::X0) |
- getRenamableRegState(SrcRenamable);
- switch (Inst.getOpndKind()) {
- case RISCVMatInt::Imm:
- BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
- .addImm(Inst.getImm());
- break;
- case RISCVMatInt::RegX0:
- BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
- .addReg(SrcReg, SrcRegState)
- .addReg(RISCV::X0);
- break;
- case RISCVMatInt::RegReg:
- BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
- .addReg(SrcReg, SrcRegState)
- .addReg(SrcReg, SrcRegState);
- break;
- case RISCVMatInt::RegImm:
- BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
- .addReg(SrcReg, SrcRegState)
- .addImm(Inst.getImm());
- break;
- }
- // Only the first instruction has X0 as its source.
- SrcReg = DstReg;
- SrcRenamable = Renamable;
- }
+
+ TII->movImm(MBB, MBBI, DL, DstReg, Val, MachineInstr::NoFlags, Renamable,
+ DstIsDead);
+
MBBI->eraseFromParent();
return true;
}
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