[llvm] [RISCV] Add copyPhysRegVector to extract common vector code out of copyPhysRegVector. (PR #70497)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 27 12:14:40 PDT 2023
================
@@ -350,176 +438,118 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
&RISCV::FPR32RegClass);
Opc = RISCV::FSGNJ_S;
}
- IsScalableVector = false;
- } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::FSGNJ_S;
- IsScalableVector = false;
- } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::FSGNJ_D;
- IsScalableVector = false;
- } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- LMul = RISCVII::LMUL_1;
- } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV2R_V;
- LMul = RISCVII::LMUL_2;
- } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV4R_V;
- LMul = RISCVII::LMUL_4;
- } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV8R_V;
- LMul = RISCVII::LMUL_8;
- } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- SubRegIdx = RISCV::sub_vrm1_0;
- NF = 2;
- LMul = RISCVII::LMUL_1;
- } else if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV2R_V;
- SubRegIdx = RISCV::sub_vrm2_0;
- NF = 2;
- LMul = RISCVII::LMUL_2;
- } else if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV4R_V;
- SubRegIdx = RISCV::sub_vrm4_0;
- NF = 2;
- LMul = RISCVII::LMUL_4;
- } else if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- SubRegIdx = RISCV::sub_vrm1_0;
- NF = 3;
- LMul = RISCVII::LMUL_1;
- } else if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV2R_V;
- SubRegIdx = RISCV::sub_vrm2_0;
- NF = 3;
- LMul = RISCVII::LMUL_2;
- } else if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- SubRegIdx = RISCV::sub_vrm1_0;
- NF = 4;
- LMul = RISCVII::LMUL_1;
- } else if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV2R_V;
- SubRegIdx = RISCV::sub_vrm2_0;
- NF = 4;
- LMul = RISCVII::LMUL_2;
- } else if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- SubRegIdx = RISCV::sub_vrm1_0;
- NF = 5;
- LMul = RISCVII::LMUL_1;
- } else if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- SubRegIdx = RISCV::sub_vrm1_0;
- NF = 6;
- LMul = RISCVII::LMUL_1;
- } else if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- SubRegIdx = RISCV::sub_vrm1_0;
- NF = 7;
- LMul = RISCVII::LMUL_1;
- } else if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
- Opc = RISCV::VMV1R_V;
- SubRegIdx = RISCV::sub_vrm1_0;
- NF = 8;
- LMul = RISCVII::LMUL_1;
- } else {
- llvm_unreachable("Impossible reg-to-reg copy");
+ BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
}
- if (IsScalableVector) {
- bool UseVMV_V_V = false;
- bool UseVMV_V_I = false;
- MachineBasicBlock::const_iterator DefMBBI;
- if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
- UseVMV_V_V = true;
- // We only need to handle LMUL = 1/2/4/8 here because we only define
- // vector register classes for LMUL = 1/2/4/8.
- unsigned VIOpc;
- switch (LMul) {
- default:
- llvm_unreachable("Impossible LMUL for vector register copy.");
- case RISCVII::LMUL_1:
- Opc = RISCV::PseudoVMV_V_V_M1;
- VIOpc = RISCV::PseudoVMV_V_I_M1;
- break;
- case RISCVII::LMUL_2:
- Opc = RISCV::PseudoVMV_V_V_M2;
- VIOpc = RISCV::PseudoVMV_V_I_M2;
- break;
- case RISCVII::LMUL_4:
- Opc = RISCV::PseudoVMV_V_V_M4;
- VIOpc = RISCV::PseudoVMV_V_I_M4;
- break;
- case RISCVII::LMUL_8:
- Opc = RISCV::PseudoVMV_V_V_M8;
- VIOpc = RISCV::PseudoVMV_V_I_M8;
- break;
- }
-
- if (DefMBBI->getOpcode() == VIOpc) {
- UseVMV_V_I = true;
- Opc = VIOpc;
- }
- }
-
- if (NF == 1) {
- auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
- if (UseVMV_V_V)
- MIB.addReg(DstReg, RegState::Undef);
- if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
- else
- MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
- if (UseVMV_V_V) {
- const MCInstrDesc &Desc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0); // tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
- }
- } else {
- int I = 0, End = NF, Incr = 1;
- unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
- unsigned DstEncoding = TRI->getEncodingValue(DstReg);
- unsigned LMulVal;
- bool Fractional;
- std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
- assert(!Fractional && "It is impossible be fractional lmul here.");
- if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
- I = NF - 1;
- End = -1;
- Incr = -1;
- }
+ if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
- for (; I != End; I += Incr) {
- auto MIB = BuildMI(MBB, MBBI, DL, get(Opc),
- TRI->getSubReg(DstReg, SubRegIdx + I));
- if (UseVMV_V_V)
- MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I),
- RegState::Undef);
- if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
- else
- MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
- getKillRegState(KillSrc));
- if (UseVMV_V_V) {
- const MCInstrDesc &Desc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0); // tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
- }
- }
- }
- } else {
- BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
+ if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_D), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+
+ // VR->VR copies.
+ if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
+ copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
+ /*NF=*/1, RISCVII::LMUL_1, RISCV::sub_vrm1_0);
+ return;
+ }
+
+ if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
+ copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
+ /*NF=*/1, RISCVII::LMUL_2, RISCV::sub_vrm1_0);
----------------
topperc wrote:
Note the SubRegIdx parameter is only used when NF != 1, so its value doesn't matter. The original code used sub_vrm1_0 for NF==1. There is no sub_vrm8_0 so we can't make it match the LMUL for NF=1.
https://github.com/llvm/llvm-project/pull/70497
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