[llvm] 3e6d6f2 - [AMDGPU] Set Size to 4 for V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO (#70376)

[via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2023-10-27T10:22:54-07:00
New Revision: 3e6d6f2834b65bf18e7c8824133e647821a02207

URL: https://github.com/llvm/llvm-project/commit/3e6d6f2834b65bf18e7c8824133e647821a02207
DIFF: https://github.com/llvm/llvm-project/commit/3e6d6f2834b65bf18e7c8824133e647821a02207.diff

LOG: [AMDGPU] Set Size to 4 for V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO (#70376)

These are not fixed size instructions, so immediate size shall be added
separately. A minimal opcode size 4 since the inception of the V_MOV_B64
instruction. A real instruction can be as small as 4 bytes in case of
inline immediate. Otherwise it is NFCI.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e7eb24033bea9b1..3cd0821b0f86c5f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -132,7 +132,7 @@ def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
   let isAsCheapAsAMove = 1;
   let isMoveImm = 1;
   let SchedRW = [Write64Bit];
-  let Size = 16; // Needs maximum 2 v_mov_b32 instructions 8 byte long each.
+  let Size = 4;
   let UseNamedOperandTable = 1;
 }
 
@@ -149,7 +149,7 @@ def S_MOV_B64_IMM_PSEUDO : SPseudoInstSI <(outs SReg_64:$sdst),
   let isAsCheapAsAMove = 1;
   let isMoveImm = 1;
   let SchedRW = [WriteSALU, Write64Bit];
-  let Size = 16; // Needs maximum 2 s_mov_b32 instructions 8 byte long each.
+  let Size = 4;
   let Uses = [];
   let UseNamedOperandTable = 1;
 }