[llvm] 58bdd16 - [ARM] Add a test for incorrect demand bits / undef fold. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2023-10-27T16:38:46+01:00
New Revision: 58bdd165d505f3993d15442afd2286c4deedcba2

URL: https://github.com/llvm/llvm-project/commit/58bdd165d505f3993d15442afd2286c4deedcba2
DIFF: https://github.com/llvm/llvm-project/commit/58bdd165d505f3993d15442afd2286c4deedcba2.diff

LOG: [ARM] Add a test for incorrect demand bits / undef fold. NFC

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/ARM/mve-narrow.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/ARM/mve-narrow.ll b/llvm/test/Transforms/InstCombine/ARM/mve-narrow.ll
index 623e774ea2c31ac..20babc29d535ec2 100644
--- a/llvm/test/Transforms/InstCombine/ARM/mve-narrow.ll
+++ b/llvm/test/Transforms/InstCombine/ARM/mve-narrow.ll
@@ -241,6 +241,30 @@ define <8 x half> @test_cvtnp_v8i16_bt(<8 x half> %a, <8 x half> %b, <4 x float>
   ret <8 x half> %z
 }
 
+define <4 x i32> @test_vshrn_const(<8 x i16> %a) {
+; CHECK-LABEL: @test_vshrn_const(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %y = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %a, <4 x i32> <i32 512, i32 0, i32 0, i32 0>, i32 3, i32 0, i32 0, i32 0, i32 0, i32 1)
+  %z = shufflevector <8 x i16> %y, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %za = zext <4 x i16> %z to <4 x i32>
+  ret <4 x i32> %za
+}
+
+define zeroext i16 @test_undef_bits() {
+; CHECK-LABEL: @test_undef_bits(
+; CHECK-NEXT:  e:
+; CHECK-NEXT:    ret i16 0
+;
+e:
+  %0 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> zeroinitializer, <4 x i32> <i32 256, i32 0, i32 0, i32 0>, i32 8, i32 1, i32 1, i32 1, i32 0, i32 1)
+  %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %2 = zext <4 x i16> %1 to <4 x i32>
+  %3 = bitcast <4 x i32> %2 to <8 x i16>
+  %4 = extractelement <8 x i16> %3, i32 0
+  ret i16 %4
+}
+
 declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32)
 declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>)
 declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32)