[llvm] [AMDGPU] GCNRegPressure printing pass for testing. (PR #70031)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 27 06:13:17 PDT 2023
================
@@ -0,0 +1,388 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null --run-pass=amdgpu-print-rp %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPU
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null --run-pass=amdgpu-print-rp -amdgpu-print-rp-downward %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPD
+
+
+---
+name: trivial
+tracksRegLiveness: true
+body: |
+ ; RP-LABEL: name: trivial
+ ; RP: bb.0:
+ ; RP-NEXT: Live-in:
+ ; RP-NEXT: SGPR VGPR
+ ; RP-NEXT: 0 0
+ ; RP-NEXT: 0 1 %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
+ ; RP-NEXT: 0 1
+ ; RP-NEXT: 2 1 %1:sgpr_64 = IMPLICIT_DEF
+ ; RP-NEXT: 2 1
+ ; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: Live-thr:
+ ; RP-NEXT: bb.1:
+ ; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: SGPR VGPR
+ ; RP-NEXT: 2 1
+ ; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: bb.2:
+ ; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F
+ ; RP-NEXT: SGPR VGPR
+ ; RP-NEXT: 2 1
+ ; RP-NEXT: 2 1 S_NOP 0, implicit %0:vgpr_32, implicit %1:sgpr_64
+ ; RP-NEXT: 0 0
+ ; RP-NEXT: Live-out:
+ ; RP-NEXT: Live-thr:
+ bb.0:
+ %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
+ %1:sgpr_64 = IMPLICIT_DEF
+ bb.1:
+
+ bb.2:
+ S_NOP 0, implicit %0, implicit %1
+...
+
+# This testcase shows the problem with LiveIntervals: it doesn't create
+# subranges for undefined but used subregisters. Upward tracker is able to see
+# the use of undefined subregister and tracks it correctly.
+---
+name: upward_problem_lis_subregs_mismatch
+tracksRegLiveness: true
+body: |
+ ; RPU-LABEL: name: upward_problem_lis_subregs_mismatch
+ ; RPU: bb.0:
+ ; RPU-NEXT: Live-in:
+ ; RPU-NEXT: SGPR VGPR
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 1 undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec
+ ; RPU-NEXT: 0 1
+ ; RPU-NEXT: 0 2 undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
+ ; RPU-NEXT: 0 2
+ ; RPU-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: Live-thr:
+ ; RPU-NEXT: bb.1:
+ ; RPU-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: SGPR VGPR
+ ; RPU-NEXT: 0 2
+ ; RPU-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: bb.2:
+ ; RPU-NEXT: Live-in: %0:000000000000000F %1:000000000000000F
+ ; RPU-NEXT: mis LIS: %0:0000000000000003 %1:000000000000000C
+ ; RPU-NEXT: %0 masks doesn't match: LIS reported 0000000000000003, tracked 000000000000000F
+ ; RPU-NEXT: %1 masks doesn't match: LIS reported 000000000000000C, tracked 000000000000000F
+ ; RPU-NEXT: SGPR VGPR
+ ; RPU-NEXT: 0 4
+ ; RPU-NEXT: 0 4 S_NOP 0, implicit %0:vreg_64, implicit %1:vreg_64
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: Live-out:
+ ; RPU-NEXT: Live-thr:
+ ;
+ ; RPD-LABEL: name: upward_problem_lis_subregs_mismatch
+ ; RPD: bb.0:
+ ; RPD-NEXT: Live-in:
+ ; RPD-NEXT: SGPR VGPR
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: 0 1 undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec
+ ; RPD-NEXT: 0 1
+ ; RPD-NEXT: 0 2 undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
+ ; RPD-NEXT: 0 2
+ ; RPD-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: Live-thr:
+ ; RPD-NEXT: bb.1:
+ ; RPD-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: SGPR VGPR
+ ; RPD-NEXT: 0 2
+ ; RPD-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: bb.2:
+ ; RPD-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C
+ ; RPD-NEXT: SGPR VGPR
+ ; RPD-NEXT: 0 2
+ ; RPD-NEXT: 0 2 S_NOP 0, implicit %0:vreg_64, implicit %1:vreg_64
+ ; RPD-NEXT: 0 0
+ ; RPD-NEXT: Live-out:
+ ; RPD-NEXT: Live-thr:
+ bb.0:
+ undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec
+ undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec
+
+ bb.1:
+
+ bb.2:
+ S_NOP 0, implicit %0, implicit %1
+...
+---
+name: only_dbg_value_sched_region
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ waveLimiter: true
+body: |
+ ; RPU-LABEL: name: only_dbg_value_sched_region
+ ; RPU: bb.0:
+ ; RPU-NEXT: Live-in:
+ ; RPU-NEXT: SGPR VGPR
+ ; RPU-NEXT: 0 0
+ ; RPU-NEXT: 0 1 %0:vgpr_32 = COPY $vgpr0
+ ; RPU-NEXT: 0 1
+ ; RPU-NEXT: 0 3 %1:vreg_64 = IMPLICIT_DEF
+ ; RPU-NEXT: 0 3
+ ; RPU-NEXT: 0 5 %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1:vreg_64, 0, 0, implicit $exec
+ ; RPU-NEXT: 0 5
+ ; RPU-NEXT: 0 6 %3:vgpr_32 = GLOBAL_LOAD_DWORD %1:vreg_64, 8, 0, implicit $exec
+ ; RPU-NEXT: 0 6
+ ; RPU-NEXT: 0 7 undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0:vgpr_32, %0:vgpr_32, implicit $exec
+ ; RPU-NEXT: 0 7
+ ; RPU-NEXT: 0 8 %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
+ ; RPU-NEXT: 0 8
+ ; RPU-NEXT: 0 10 %5:vreg_64 = COPY %2:vreg_64
----------------
jayfoad wrote:
RPU and RPD are both wrong here. Pressure "at" this instruction should be 9.
https://github.com/llvm/llvm-project/pull/70031
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