[llvm] 8e247b8 - Replace TypeSize::{getFixed,getScalable} with canonical TypeSize::{Fixed,Scalable}. NFC
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 27 00:30:46 PDT 2023
Author: Fangrui Song
Date: 2023-10-27T00:30:41-07:00
New Revision: 8e247b8f4734b1b829156794bb2d9bf8c9c0e72a
URL: https://github.com/llvm/llvm-project/commit/8e247b8f4734b1b829156794bb2d9bf8c9c0e72a
DIFF: https://github.com/llvm/llvm-project/commit/8e247b8f4734b1b829156794bb2d9bf8c9c0e72a.diff
LOG: Replace TypeSize::{getFixed,getScalable} with canonical TypeSize::{Fixed,Scalable}. NFC
Added:
Modified:
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/include/llvm/CodeGen/BasicTTIImpl.h
llvm/lib/Analysis/BasicAliasAnalysis.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/IR/DebugInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
llvm/lib/Target/DirectX/CBufferDataLayout.cpp
llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
llvm/lib/Target/VE/VETargetTransformInfo.h
llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
llvm/lib/Transforms/Utils/Local.cpp
llvm/unittests/CodeGen/LowLevelTypeTest.cpp
llvm/unittests/IR/InstructionsTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index c1ff314ae51c98b..e14915443513990 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -443,7 +443,7 @@ class TargetTransformInfoImplBase {
}
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
- return TypeSize::getFixed(32);
+ return TypeSize::Fixed(32);
}
unsigned getMinVectorRegisterBitWidth() const { return 128; }
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 752b554d6989919..7a8f36da58ceccb 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -714,7 +714,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
/// @{
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
- return TypeSize::getFixed(32);
+ return TypeSize::Fixed(32);
}
std::optional<unsigned> getMaxVScale() const { return std::nullopt; }
diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index 2acd5c47b7681e8..f70b39b4f51a77a 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -111,7 +111,7 @@ static std::optional<TypeSize> getObjectSize(const Value *V,
Opts.RoundToAlign = RoundToAlign;
Opts.NullIsUnknownSize = NullIsValidLoc;
if (getObjectSize(V, Size, DL, &TLI, Opts))
- return TypeSize::getFixed(Size);
+ return TypeSize::Fixed(Size);
return std::nullopt;
}
@@ -177,7 +177,7 @@ static TypeSize getMinimalExtentFrom(const Value &V,
// accessed, thus valid.
if (LocSize.isPrecise())
DerefBytes = std::max(DerefBytes, LocSize.getValue().getKnownMinValue());
- return TypeSize::getFixed(DerefBytes);
+ return TypeSize::Fixed(DerefBytes);
}
/// Returns true if we can prove that the object specified by V has size Size.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index fc9e3ff3734989d..5bd04e2360679d4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -4422,7 +4422,7 @@ void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
// FIXME: should we be more picky about alignment?
Align StackSlotAlignment(1);
SDValue StackPtr = DAG.CreateStackTemporary(
- TypeSize::getFixed(StackSlotByteWidth), StackSlotAlignment);
+ TypeSize::Fixed(StackSlotByteWidth), StackSlotAlignment);
EVT PtrTy = StackPtr.getValueType();
SDValue Ch = DAG.getEntryNode();
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index 48b5501c55ba47d..390a27c4bc0c4dd 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -1947,7 +1947,7 @@ std::optional<AssignmentInfo> at::getAssignmentInfo(const DataLayout &DL,
// We can't use a non-const size, bail.
return std::nullopt;
uint64_t SizeInBits = 8 * ConstLengthInBytes->getZExtValue();
- return getAssignmentInfoImpl(DL, StoreDest, TypeSize::getFixed(SizeInBits));
+ return getAssignmentInfoImpl(DL, StoreDest, TypeSize::Fixed(SizeInBits));
}
std::optional<AssignmentInfo> at::getAssignmentInfo(const DataLayout &DL,
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index f121dc40e9fe6d7..5f2d09f0765aa38 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1961,21 +1961,20 @@ TypeSize
AArch64TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(64);
+ return TypeSize::Fixed(64);
case TargetTransformInfo::RGK_FixedWidthVector:
if (!ST->isNeonAvailable() && !EnableFixedwidthAutovecInStreamingMode)
- return TypeSize::getFixed(0);
+ return TypeSize::Fixed(0);
if (ST->hasSVE())
- return TypeSize::getFixed(
- std::max(ST->getMinSVEVectorSizeInBits(), 128u));
+ return TypeSize::Fixed(std::max(ST->getMinSVEVectorSizeInBits(), 128u));
- return TypeSize::getFixed(ST->hasNEON() ? 128 : 0);
+ return TypeSize::Fixed(ST->hasNEON() ? 128 : 0);
case TargetTransformInfo::RGK_ScalableVector:
if (!ST->isSVEAvailable() && !EnableScalableAutovecInStreamingMode)
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
- return TypeSize::getScalable(ST->hasSVE() ? 128 : 0);
+ return TypeSize::Scalable(ST->hasSVE() ? 128 : 0);
}
llvm_unreachable("Unsupported register kind");
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index cb877a4695f1ece..fa302b68263f7f6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -321,11 +321,11 @@ TypeSize
GCNTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(32);
+ return TypeSize::Fixed(32);
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed(ST->hasPackedFP32Ops() ? 64 : 32);
+ return TypeSize::Fixed(ST->hasPackedFP32Ops() ? 64 : 32);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
}
diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
index 1a1be4a442857be..6ca821174bd832d 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
@@ -38,7 +38,7 @@ unsigned R600TTIImpl::getNumberOfRegisters(bool Vec) const {
TypeSize
R600TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
- return TypeSize::getFixed(32);
+ return TypeSize::Fixed(32);
}
unsigned R600TTIImpl::getMinVectorRegisterBitWidth() const { return 32; }
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index bb4b321b5300916..71e8a24afc401ec 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -165,15 +165,15 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(32);
+ return TypeSize::Fixed(32);
case TargetTransformInfo::RGK_FixedWidthVector:
if (ST->hasNEON())
- return TypeSize::getFixed(128);
+ return TypeSize::Fixed(128);
if (ST->hasMVEIntegerOps())
- return TypeSize::getFixed(128);
- return TypeSize::getFixed(0);
+ return TypeSize::Fixed(128);
+ return TypeSize::Fixed(0);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
}
diff --git a/llvm/lib/Target/DirectX/CBufferDataLayout.cpp b/llvm/lib/Target/DirectX/CBufferDataLayout.cpp
index 41bb69b3d79c614..e539bfe7e6d5172 100644
--- a/llvm/lib/Target/DirectX/CBufferDataLayout.cpp
+++ b/llvm/lib/Target/DirectX/CBufferDataLayout.cpp
@@ -76,12 +76,12 @@ TypeSize LegacyCBufferLayout::getTypeAllocSize(Type *Ty) {
} else if (auto *AT = dyn_cast<ArrayType>(Ty)) {
unsigned NumElts = AT->getNumElements();
if (NumElts == 0)
- return TypeSize::getFixed(0);
+ return TypeSize::Fixed(0);
TypeSize EltSize = getTypeAllocSize(AT->getElementType());
TypeSize AlignedEltSize = alignTo4Dwords(EltSize);
// Each new element start 4 dwords aligned.
- return TypeSize::getFixed(AlignedEltSize * (NumElts - 1) + EltSize);
+ return TypeSize::Fixed(AlignedEltSize * (NumElts - 1) + EltSize);
} else {
// NOTE: Use type store size, not align to ABI on basic types for legacy
// layout.
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
index cf4b66f8bf8619b..6d4463108c1c04c 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -118,11 +118,11 @@ TypeSize
HexagonTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(32);
+ return TypeSize::Fixed(32);
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed(getMinVectorRegisterBitWidth());
+ return TypeSize::Fixed(getMinVectorRegisterBitWidth());
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
index 3ce2675560c4df0..7c90d66d6ae7d7d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
@@ -78,7 +78,7 @@ class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
// Only <2 x half> should be vectorized, so always return 32 for the vector
// register size.
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
- return TypeSize::getFixed(32);
+ return TypeSize::Fixed(32);
}
unsigned getMinVectorRegisterBitWidth() const { return 32; }
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index ca0f2c2e18af5f9..f2d7fb3e245dbb2 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -493,11 +493,11 @@ TypeSize
PPCTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(ST->isPPC64() ? 64 : 32);
+ return TypeSize::Fixed(ST->isPPC64() ? 64 : 32);
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed(ST->hasAltivec() ? 128 : 0);
+ return TypeSize::Fixed(ST->hasAltivec() ? 128 : 0);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 09f9b6035aeb06f..25bbb189cadd835 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -210,16 +210,15 @@ RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
llvm::bit_floor(std::clamp<unsigned>(RVVRegisterWidthLMUL, 1, 8));
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(ST->getXLen());
+ return TypeSize::Fixed(ST->getXLen());
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed(
+ return TypeSize::Fixed(
ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(
- (ST->hasVInstructions() &&
- ST->getRealMinVLen() >= RISCV::RVVBitsPerBlock)
- ? LMUL * RISCV::RVVBitsPerBlock
- : 0);
+ return TypeSize::Scalable((ST->hasVInstructions() &&
+ ST->getRealMinVLen() >= RISCV::RVVBitsPerBlock)
+ ? LMUL * RISCV::RVVBitsPerBlock
+ : 0);
}
llvm_unreachable("Unsupported register kind");
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index 1f97e0f761c04de..b49f223e6b68f4f 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -366,11 +366,11 @@ TypeSize
SystemZTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(64);
+ return TypeSize::Fixed(64);
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed(ST->hasVector() ? 128 : 0);
+ return TypeSize::Fixed(ST->hasVector() ? 128 : 0);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h
index c688447088782a0..8c9ef850b9581a5 100644
--- a/llvm/lib/Target/VE/VETargetTransformInfo.h
+++ b/llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -98,12 +98,12 @@ class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(64);
+ return TypeSize::Fixed(64);
case TargetTransformInfo::RGK_FixedWidthVector:
// TODO report vregs once vector isel is stable.
- return TypeSize::getFixed(0);
+ return TypeSize::Fixed(0);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
index 9a434d9b1db54a9..306db7cf7614fab 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
@@ -40,11 +40,11 @@ TypeSize WebAssemblyTTIImpl::getRegisterBitWidth(
TargetTransformInfo::RegisterKind K) const {
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(64);
+ return TypeSize::Fixed(64);
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed(getST()->hasSIMD128() ? 128 : 64);
+ return TypeSize::Fixed(getST()->hasSIMD128() ? 128 : 64);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 8a04987e768a126..3c91fc12bcdc9d1 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -178,17 +178,17 @@ X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
unsigned PreferVectorWidth = ST->getPreferVectorWidth();
switch (K) {
case TargetTransformInfo::RGK_Scalar:
- return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
+ return TypeSize::Fixed(ST->is64Bit() ? 64 : 32);
case TargetTransformInfo::RGK_FixedWidthVector:
if (ST->hasAVX512() && ST->hasEVEX512() && PreferVectorWidth >= 512)
- return TypeSize::getFixed(512);
+ return TypeSize::Fixed(512);
if (ST->hasAVX() && PreferVectorWidth >= 256)
- return TypeSize::getFixed(256);
+ return TypeSize::Fixed(256);
if (ST->hasSSE1() && PreferVectorWidth >= 128)
- return TypeSize::getFixed(128);
- return TypeSize::getFixed(0);
+ return TypeSize::Fixed(128);
+ return TypeSize::Fixed(0);
case TargetTransformInfo::RGK_ScalableVector:
- return TypeSize::getScalable(0);
+ return TypeSize::Scalable(0);
}
llvm_unreachable("Unsupported register kind");
diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
index 75490e984f98546..cacefc9718f1176 100644
--- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
@@ -214,7 +214,7 @@ static std::optional<TypeSize> getPointerSize(const Value *V,
Opts.NullIsUnknownSize = NullPointerIsDefined(F);
if (getObjectSize(V, Size, DL, &TLI, Opts))
- return TypeSize::getFixed(Size);
+ return TypeSize::Fixed(Size);
return std::nullopt;
}
diff --git a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
index b1c60d12aa1b66a..b366ec5d4c35725 100644
--- a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+++ b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
@@ -1720,7 +1720,7 @@ bool MemCpyOptPass::processMemCpy(MemCpyInst *M, BasicBlock::iterator &BBI) {
if (auto *CopySize = dyn_cast<ConstantInt>(M->getLength())) {
if (auto *C = dyn_cast<CallInst>(MI)) {
if (performCallSlotOptzn(M, M, M->getDest(), M->getSource(),
- TypeSize::getFixed(CopySize->getZExtValue()),
+ TypeSize::Fixed(CopySize->getZExtValue()),
M->getDestAlign().valueOrOne(), BAA,
[C]() -> CallInst * { return C; })) {
LLVM_DEBUG(dbgs() << "Performed call slot optimization:\n"
@@ -1766,7 +1766,7 @@ bool MemCpyOptPass::processMemCpy(MemCpyInst *M, BasicBlock::iterator &BBI) {
if (Len == nullptr)
return false;
if (performStackMoveOptzn(M, M, DestAlloca, SrcAlloca,
- TypeSize::getFixed(Len->getZExtValue()), BAA)) {
+ TypeSize::Fixed(Len->getZExtValue()), BAA)) {
// Avoid invalidating the iterator.
BBI = M->getNextNonDebugInstruction()->getIterator();
eraseInstruction(M);
@@ -1829,7 +1829,7 @@ bool MemCpyOptPass::processByValArgument(CallBase &CB, unsigned ArgNo) {
// The length of the memcpy must be larger or equal to the size of the byval.
auto *C1 = dyn_cast<ConstantInt>(MDep->getLength());
if (!C1 || !TypeSize::isKnownGE(
- TypeSize::getFixed(C1->getValue().getZExtValue()), ByValSize))
+ TypeSize::Fixed(C1->getValue().getZExtValue()), ByValSize))
return false;
// Get the alignment of the byval. If the call doesn't specify the alignment,
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 0326e17a6fa14df..a255db7dafa79d0 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -1497,7 +1497,7 @@ static bool valueCoversEntireFragment(Type *ValTy, DbgVariableIntrinsic *DII) {
const DataLayout &DL = DII->getModule()->getDataLayout();
TypeSize ValueSize = DL.getTypeAllocSizeInBits(ValTy);
if (std::optional<uint64_t> FragmentSize = DII->getFragmentSizeInBits())
- return TypeSize::isKnownGE(ValueSize, TypeSize::getFixed(*FragmentSize));
+ return TypeSize::isKnownGE(ValueSize, TypeSize::Fixed(*FragmentSize));
// We can't always calculate the size of the DI variable (e.g. if it is a
// VLA). Try to use the size of the alloca that the dbg intrinsic describes
diff --git a/llvm/unittests/CodeGen/LowLevelTypeTest.cpp b/llvm/unittests/CodeGen/LowLevelTypeTest.cpp
index cd55dc273e19d77..7b13fef23ed00a8 100644
--- a/llvm/unittests/CodeGen/LowLevelTypeTest.cpp
+++ b/llvm/unittests/CodeGen/LowLevelTypeTest.cpp
@@ -382,8 +382,8 @@ static_assert(CEV2P1.isVector());
static_assert(CEV2P1.getElementCount() == ElementCount::getFixed(2));
static_assert(CEV2P1.getElementCount() != ElementCount::getFixed(1));
static_assert(CEV2S32.getElementCount() == ElementCount::getFixed(2));
-static_assert(CEV2S32.getSizeInBits() == TypeSize::getFixed(64));
-static_assert(CEV2P1.getSizeInBits() == TypeSize::getFixed(128));
+static_assert(CEV2S32.getSizeInBits() == TypeSize::Fixed(64));
+static_assert(CEV2P1.getSizeInBits() == TypeSize::Fixed(128));
static_assert(CEV2P1.getScalarType() == LLT::pointer(1, 64));
static_assert(CES32.getScalarType() == CES32);
static_assert(CEV2S32.getScalarType() == CES32);
diff --git a/llvm/unittests/IR/InstructionsTest.cpp b/llvm/unittests/IR/InstructionsTest.cpp
index 20b8529b386324f..803bc56bd6d530f 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -1746,14 +1746,14 @@ TEST(InstructionsTest, AllocaInst) {
AllocaInst &F = cast<AllocaInst>(*It++);
AllocaInst &G = cast<AllocaInst>(*It++);
AllocaInst &H = cast<AllocaInst>(*It++);
- EXPECT_EQ(A.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
- EXPECT_EQ(B.getAllocationSizeInBits(DL), TypeSize::getFixed(128));
+ EXPECT_EQ(A.getAllocationSizeInBits(DL), TypeSize::Fixed(32));
+ EXPECT_EQ(B.getAllocationSizeInBits(DL), TypeSize::Fixed(128));
EXPECT_FALSE(C.getAllocationSizeInBits(DL));
- EXPECT_EQ(D.getAllocationSizeInBits(DL), TypeSize::getFixed(512));
- EXPECT_EQ(E.getAllocationSizeInBits(DL), TypeSize::getScalable(512));
- EXPECT_EQ(F.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
- EXPECT_EQ(G.getAllocationSizeInBits(DL), TypeSize::getFixed(768));
- EXPECT_EQ(H.getAllocationSizeInBits(DL), TypeSize::getFixed(160));
+ EXPECT_EQ(D.getAllocationSizeInBits(DL), TypeSize::Fixed(512));
+ EXPECT_EQ(E.getAllocationSizeInBits(DL), TypeSize::Scalable(512));
+ EXPECT_EQ(F.getAllocationSizeInBits(DL), TypeSize::Fixed(32));
+ EXPECT_EQ(G.getAllocationSizeInBits(DL), TypeSize::Fixed(768));
+ EXPECT_EQ(H.getAllocationSizeInBits(DL), TypeSize::Fixed(160));
}
TEST(InstructionsTest, InsertAtBegin) {
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