[llvm] [RISCV] Add `TuneVentanaVeyron` subtarget feature. (PR #70414)

[Craig Topper via llvm-commits]

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@@ -46,10 +46,7 @@ struct RISCVTuneInfo {
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
 public:
-  enum RISCVProcFamilyEnum : uint8_t {
-    Others,
-    SiFive7,
-  };
+  enum RISCVProcFamilyEnum : uint8_t { Others, SiFive7, VentanaVeyron };
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topperc wrote:

Please don't reformat this. I have other CPUs in this enum in my downstream. I'd prefer to keep one CPU per line. We can put a clang-format off/on around it.

https://github.com/llvm/llvm-project/pull/70414