[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)

[Mikhail Gudim via llvm-commits]

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@@ -242,4 +242,5 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
                                              FeatureStdExtZicbom,
                                              FeatureStdExtZicbop,
                                              FeatureStdExtZicboz,
-                                             FeatureVendorXVentanaCondOps]>;
+                                             FeatureVendorXVentanaCondOps,
+                                             TuneVeyronFusions]>;
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mgudim wrote:

done in https://github.com/llvm/llvm-project/pull/70414

https://github.com/llvm/llvm-project/pull/70012