[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)

[Mikhail Gudim via llvm-commits]

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@@ -954,6 +964,14 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
                                    [TuneNoDefaultUnroll,
                                     TuneShortForwardBranchOpt]>;
 
+def TuneVeyronFusions : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
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mgudim wrote:

done: https://github.com/llvm/llvm-project/pull/70414

https://github.com/llvm/llvm-project/pull/70012