[llvm] [RISCV] Add `TuneVentanaVeyron` subtarget feature. (PR #70414)

[Mikhail Gudim via llvm-commits]

https://github.com/mgudim created https://github.com/llvm/llvm-project/pull/70414

This will be used to add veyron fusions in a later commit.

>From 22bc1b1f9e24922d621da6d50990050fbe6c996f Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim at gmail.com>
Date: Thu, 26 Oct 2023 22:30:01 -0400
Subject: [PATCH] [RISCV] Add `TuneVentanaVeyron` subtarget feature.

This will be used to add veyron fusions in a later commit.
---
 llvm/lib/Target/RISCV/RISCVFeatures.td   | 4 ++++
 llvm/lib/Target/RISCV/RISCVProcessors.td | 3 ++-
 llvm/lib/Target/RISCV/RISCVSubtarget.h   | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 979bc0ea8c7d065..ba6c63d8958e647 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -954,6 +954,10 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
                                    [TuneNoDefaultUnroll,
                                     TuneShortForwardBranchOpt]>;
 
+def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
+                                         "Ventana-Veyron Series processors",
+                                         [TuneLUIADDIFusion]>;
+
 // Assume that lock-free native-width atomics are available, even if the target
 // and operating system combination would not usually provide them. The user
 // is responsible for providing any necessary __sync implementations. Code
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e4008d145ffa572..5465e0c998ca6f8 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -242,4 +242,5 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
                                              FeatureStdExtZicbom,
                                              FeatureStdExtZicbop,
                                              FeatureStdExtZicboz,
-                                             FeatureVendorXVentanaCondOps]>;
+                                             FeatureVendorXVentanaCondOps],
+                                             [TuneVentanaVeyron]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 6b915e61c136086..cfd59bdcfa5fda6 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -49,6 +49,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   enum RISCVProcFamilyEnum : uint8_t {
     Others,
     SiFive7,
+    VentanaVeyron
   };
 
 private: