[llvm] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 26 19:25:32 PDT 2023
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@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
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MaskRay wrote:
Sometimes checking that there is no unrelated feature is important. `linux-cross.cpp` `// DEBIAN_I686_M64-SAME: {{^}} ` provides an example. But here it may not be important.
https://github.com/llvm/llvm-project/pull/70294
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