[llvm] [AMDGPU] Select 64-bit moves (PR #70395)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

> ⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️
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> View the diff from clang-format here.
> 
> ```diff
> diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
> index 284943eae465..f62e273253e6 100644
> --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
> +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
> @@ -1094,23 +1094,23 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
>        Register DstSubReg = RI.getSubReg(DestReg, SubIdx);
>        Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
>        MachineInstrBuilder MIB =
> -        BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DstSubReg)
> -        .addImm(SISrcMods::OP_SEL_1)
> -        .addReg(SrcSubReg)
> -        .addImm(SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1)
> -        .addReg(SrcSubReg)
> -        .addImm(0) // op_sel_lo
> -        .addImm(0) // op_sel_hi
> -        .addImm(0) // neg_lo
> -        .addImm(0) // neg_hi
> -        .addImm(0) // clamp
> -        .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
> +          BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DstSubReg)
> +              .addImm(SISrcMods::OP_SEL_1)
> +              .addReg(SrcSubReg)
> +              .addImm(SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1)
> +              .addReg(SrcSubReg)
> +              .addImm(0) // op_sel_lo
> +              .addImm(0) // op_sel_hi
> +              .addImm(0) // neg_lo
> +              .addImm(0) // neg_hi
> +              .addImm(0) // clamp
> +              .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
>        if (IsFirstSubreg)
>          MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
>      } else {
>        MachineInstrBuilder Builder =
> -        BuildMI(MBB, MI, DL, get(Opcode), RI.getSubReg(DestReg, SubIdx))
> -        .addReg(RI.getSubReg(SrcReg, SubIdx));
> +          BuildMI(MBB, MI, DL, get(Opcode), RI.getSubReg(DestReg, SubIdx))
> +              .addReg(RI.getSubReg(SrcReg, SubIdx));
>        if (IsFirstSubreg)
>          Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
>  
> @@ -5308,13 +5308,10 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
>    MO.ChangeToRegister(Reg, false);
>  }
>  
> -unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
> -                                         MachineRegisterInfo &MRI,
> -                                         MachineOperand &SuperReg,
> -                                         const TargetRegisterClass *SuperRC,
> -                                         unsigned SubIdx,
> -                                         const TargetRegisterClass *SubRC)
> -                                         const {
> +unsigned SIInstrInfo::buildExtractSubReg(
> +    MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
> +    MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
> +    unsigned SubIdx, const TargetRegisterClass *SubRC) const {
>    MachineBasicBlock *MBB = MI->getParent();
>    DebugLoc DL = MI->getDebugLoc();
>    Register SubReg = MRI.createVirtualRegister(SubRC);
> @@ -5341,12 +5338,9 @@ unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
>  }
>  
>  MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
> -  MachineBasicBlock::iterator MII,
> -  MachineRegisterInfo &MRI,
> -  MachineOperand &Op,
> -  const TargetRegisterClass *SuperRC,
> -  unsigned SubIdx,
> -  const TargetRegisterClass *SubRC) const {
> +    MachineBasicBlock::iterator MII, MachineRegisterInfo &MRI,
> +    MachineOperand &Op, const TargetRegisterClass *SuperRC, unsigned SubIdx,
> +    const TargetRegisterClass *SubRC) const {
>    if (Op.isImm()) {
>      if (SubIdx == AMDGPU::sub0)
>        return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
> ```

I didn't touch that. Github needs to do better.

https://github.com/llvm/llvm-project/pull/70395