[llvm] [AMDGPU] Set Size to 4 for V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO (PR #70376)

[Stanislav Mekhanoshin via llvm-commits]

https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/70376

These are not fixed size instructions, so immediate size shall be added separately. A minimal opcode size 4 since the inception of the V_MOV_B64 instruction. A real instruction can be as small as 4 bytes in case of inline immediate. Otherwise it is NFCI.

>From 6fb00c3f33a04b0438f8a5cc6f581fe2cf6ce8bd Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Thu, 26 Oct 2023 13:27:23 -0700
Subject: [PATCH] [AMDGPU] Set Size to 4 for V_MOV_B64_PSEUDO and
 S_MOV_B64_IMM_PSEUDO

These are not fixed size instructions, so immediate size shall
be added separately. A minimal opcode size 4 since the inception
of the V_MOV_B64 instruction. A real instruction can be as small
as 4 bytes in case of inline immediate. Otherwise it is NFCI.
---
 llvm/lib/Target/AMDGPU/SIInstructions.td | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 567f1b812c1808c..bab74c170ab399d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -132,7 +132,7 @@ def V_MOV_B64_PSEUDO : VPseudoInstSI <(outs VReg_64:$vdst),
   let isAsCheapAsAMove = 1;
   let isMoveImm = 1;
   let SchedRW = [Write64Bit];
-  let Size = 16; // Needs maximum 2 v_mov_b32 instructions 8 byte long each.
+  let Size = 4;
   let UseNamedOperandTable = 1;
 }
 
@@ -149,7 +149,7 @@ def S_MOV_B64_IMM_PSEUDO : SPseudoInstSI <(outs SReg_64:$sdst),
   let isAsCheapAsAMove = 1;
   let isMoveImm = 1;
   let SchedRW = [WriteSALU, Write64Bit];
-  let Size = 16; // Needs maximum 2 s_mov_b32 instructions 8 byte long each.
+  let Size = 4;
   let Uses = [];
   let UseNamedOperandTable = 1;
 }