[llvm] [AMDGPU] Prevent folding of the negative i32 literals as i64 (PR #70274)

[Stanislav Mekhanoshin via llvm-commits]

================
@@ -5500,6 +5500,15 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
     if (Is64BitOp && !AMDGPU::isValid32BitLiteral(Imm, Is64BitFPOp) &&
         !AMDGPU::isInlinableLiteral64(Imm, ST.hasInv2PiInlineImm()))
       return false;
+
+    // FIXME: We can use sign extended 64-bit literals, but only for signed
+    //        operands. At the moment we do not know if an operand is signed.
+    //        Such operand will be encoded as its low 32 bits and then either
+    //        correctly sign extended or incorrectly zero extended by HW.
+    if (Is64BitOp && !Is64BitFPOp && isInt<32>(Imm) &&
----------------
rampitec wrote:

Well, I guess this folding is illegal too:
```
    %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 4294967295
    %1:sreg_64 = S_ASHR_I64 %0, 1, implicit-def $scc
```
Quite unfortunately it is impossible to distinguish I32 and B32 operands here.

https://github.com/llvm/llvm-project/pull/70274