[llvm] aaabf50 - [AArch64] Regenerate tests to show missing constant comments
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 26 07:35:47 PDT 2023
Author: Simon Pilgrim
Date: 2023-10-26T15:35:17+01:00
New Revision: aaabf50d521550c0f6c0b5c8623450eb56f485f5
URL: https://github.com/llvm/llvm-project/commit/aaabf50d521550c0f6c0b5c8623450eb56f485f5
DIFF: https://github.com/llvm/llvm-project/commit/aaabf50d521550c0f6c0b5c8623450eb56f485f5.diff
LOG: [AArch64] Regenerate tests to show missing constant comments
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
llvm/test/CodeGen/AArch64/arm64-build-vector.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll b/llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
index d943afb23c03b2e..1b22514a59d6082 100644
--- a/llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
@@ -64,37 +64,37 @@ define i32 @main() nounwind ssp {
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
-; CHECK-NEXT: mov w9, #1
-; CHECK-NEXT: mov w8, #2
+; CHECK-NEXT: mov w9, #1 ; =0x1
+; CHECK-NEXT: mov w8, #2 ; =0x2
; CHECK-NEXT: stp w8, w9, [sp, #72]
-; CHECK-NEXT: mov w9, #3
-; CHECK-NEXT: mov w8, #4
+; CHECK-NEXT: mov w9, #3 ; =0x3
+; CHECK-NEXT: mov w8, #4 ; =0x4
; CHECK-NEXT: stp w8, w9, [sp, #64]
-; CHECK-NEXT: mov w9, #5
-; CHECK-NEXT: mov w8, #6
+; CHECK-NEXT: mov w9, #5 ; =0x5
+; CHECK-NEXT: mov w8, #6 ; =0x6
; CHECK-NEXT: stp w8, w9, [sp, #56]
-; CHECK-NEXT: mov w9, #7
-; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: mov w9, #7 ; =0x7
+; CHECK-NEXT: mov w8, #8 ; =0x8
; CHECK-NEXT: stp w8, w9, [sp, #48]
-; CHECK-NEXT: mov w8, #9
-; CHECK-NEXT: mov w9, #10
+; CHECK-NEXT: mov w8, #9 ; =0x9
+; CHECK-NEXT: mov w9, #10 ; =0xa
; CHECK-NEXT: stp w9, w8, [sp, #40]
-; CHECK-NEXT: mov w10, #11
-; CHECK-NEXT: mov w11, #12
+; CHECK-NEXT: mov w10, #11 ; =0xb
+; CHECK-NEXT: mov w11, #12 ; =0xc
; CHECK-NEXT: stp w11, w10, [sp, #32]
; CHECK-NEXT: stp x10, x11, [sp, #16]
; CHECK-NEXT: str x9, [sp, #8]
; CHECK-NEXT: str w8, [sp]
; CHECK-NEXT: add x0, sp, #76
-; CHECK-NEXT: mov w1, #2
-; CHECK-NEXT: mov w2, #3
-; CHECK-NEXT: mov w3, #4
-; CHECK-NEXT: mov w4, #5
-; CHECK-NEXT: mov w5, #6
-; CHECK-NEXT: mov w6, #7
-; CHECK-NEXT: mov w7, #8
+; CHECK-NEXT: mov w1, #2 ; =0x2
+; CHECK-NEXT: mov w2, #3 ; =0x3
+; CHECK-NEXT: mov w3, #4 ; =0x4
+; CHECK-NEXT: mov w4, #5 ; =0x5
+; CHECK-NEXT: mov w5, #6 ; =0x6
+; CHECK-NEXT: mov w6, #7 ; =0x7
+; CHECK-NEXT: mov w7, #8 ; =0x8
; CHECK-NEXT: bl _fn9
-; CHECK-NEXT: mov w0, #0
+; CHECK-NEXT: mov w0, #0 ; =0x0
; CHECK-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/arm64-build-vector.ll b/llvm/test/CodeGen/AArch64/arm64-build-vector.ll
index f9f57e662d6ae95..68c56d765cbb9b1 100644
--- a/llvm/test/CodeGen/AArch64/arm64-build-vector.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-build-vector.ll
@@ -24,7 +24,7 @@ define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
; CHECK-LABEL: build_all_zero:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #44672
+; CHECK-NEXT: mov w8, #44672 // =0xae80
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
@@ -56,7 +56,7 @@ define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) {
define void @widen_f16_build_vector(ptr %addr) {
; CHECK-LABEL: widen_f16_build_vector:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #13294
+; CHECK-NEXT: mov w8, #13294 // =0x33ee
; CHECK-NEXT: movk w8, #13294, lsl #16
; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: ret
@@ -68,7 +68,7 @@ define void @widen_f16_build_vector(ptr %addr) {
define <1 x i64> @single_element_vector_i64(<1 x i64> %arg) {
; CHECK-LABEL: single_element_vector_i64:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: add d0, d0, d1
; CHECK-NEXT: ret
@@ -94,7 +94,7 @@ define <1 x double> @convert_single_fp_vector_constant(i1 %cmp) {
; CHECK-LABEL: convert_single_fp_vector_constant:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: tst w0, #0x1
-; CHECK-NEXT: mov x8, #4607182418800017408
+; CHECK-NEXT: mov x8, #4607182418800017408 // =0x3ff0000000000000
; CHECK-NEXT: csetm x9, ne
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: fmov d1, x9
@@ -120,7 +120,7 @@ define <2 x double> @poszero_v2f64(<2 x double> %a) {
define <2 x double> @negzero_v2f64(<2 x double> %a) {
; CHECK-LABEL: negzero_v2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-9223372036854775808
+; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: fmul v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
@@ -141,7 +141,7 @@ define <1 x double> @poszero_v1f64(<1 x double> %a) {
define <1 x double> @negzero_v1f64(<1 x double> %a) {
; CHECK-LABEL: negzero_v1f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-9223372036854775808
+; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: fmul d0, d0, d1
; CHECK-NEXT: ret
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