[llvm] bb2b753 - [AMDGPU] precommit lit test for PR 69924.
Christudasan Devadasan via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 26 05:15:52 PDT 2023
Author: Christudasan Devadasan
Date: 2023-10-26T17:43:14+05:30
New Revision: bb2b7530adc87dabc782141573ca063b1b76ce9e
URL: https://github.com/llvm/llvm-project/commit/bb2b7530adc87dabc782141573ca063b1b76ce9e
DIFF: https://github.com/llvm/llvm-project/commit/bb2b7530adc87dabc782141573ca063b1b76ce9e.diff
LOG: [AMDGPU] precommit lit test for PR 69924.
Added:
llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll b/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
new file mode 100644
index 000000000000000..a844b577c842fba
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -O0 -verify-machineinstrs --stop-after=regallocfast,1 -o - %s | FileCheck -check-prefix=REGALLOC %s
+
+; FIXME: There are two spill codes inserted wrongly in this test.
+; They are inserted during regalloc for the BBLiveIns - the spill restores for vgpr1 in the Flow block (bb.1) and for vgpr0 in the return block (bb.4).
+define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) {
+ ; REGALLOC-LABEL: name: prolog_spill
+ ; REGALLOC: bb.0.bb.0:
+ ; REGALLOC-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
+ ; REGALLOC-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: renamable $vgpr3 = IMPLICIT_DEF
+ ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr2, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.4, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; REGALLOC-NEXT: renamable $vgpr1 = COPY killed $vgpr0
+ ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
+ ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 49
+ ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = V_CMP_GT_I32_e64 killed $vgpr1, killed $sgpr4, implicit $exec
+ ; REGALLOC-NEXT: renamable $sgpr6 = IMPLICIT_DEF
+ ; REGALLOC-NEXT: renamable $vgpr1 = COPY killed renamable $sgpr6
+ ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = COPY $exec, implicit-def $exec
+ ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 renamable $sgpr6_sgpr7, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
+ ; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = S_XOR_B64 renamable $sgpr4_sgpr5, killed renamable $sgpr6_sgpr7, implicit-def dead $scc
+ ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 killed $sgpr6, 0, $vgpr0, implicit-def $sgpr6_sgpr7, implicit $sgpr6_sgpr7
+ ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 killed $sgpr7, 1, $vgpr0, implicit killed $sgpr6_sgpr7
+ ; REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr0, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; REGALLOC-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr4_sgpr5
+ ; REGALLOC-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
+ ; REGALLOC-NEXT: S_BRANCH %bb.3
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: bb.1.Flow:
+ ; REGALLOC-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
+ ; REGALLOC-NEXT: $vgpr1 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
+ ; REGALLOC-NEXT: $sgpr4 = V_READLANE_B32 $vgpr0, 0, implicit-def $sgpr4_sgpr5
+ ; REGALLOC-NEXT: $sgpr5 = V_READLANE_B32 $vgpr0, 1
+ ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 killed renamable $sgpr4_sgpr5, implicit-def $exec, implicit-def dead $scc, implicit $exec
+ ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
+ ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 killed $sgpr4, 2, $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
+ ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 $sgpr5, 3, $vgpr0, implicit $sgpr4_sgpr5
+ ; REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr0, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; REGALLOC-NEXT: $exec = S_XOR_B64_term $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
+ ; REGALLOC-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
+ ; REGALLOC-NEXT: S_BRANCH %bb.2
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: bb.2.bb.1:
+ ; REGALLOC-NEXT: successors: %bb.4(0x80000000)
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
+ ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 10
+ ; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec
+ ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; REGALLOC-NEXT: S_BRANCH %bb.4
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: bb.3.bb.2:
+ ; REGALLOC-NEXT: successors: %bb.1(0x80000000)
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5)
+ ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 20
+ ; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec
+ ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; REGALLOC-NEXT: S_BRANCH %bb.1
+ ; REGALLOC-NEXT: {{ $}}
+ ; REGALLOC-NEXT: bb.4.bb.3:
+ ; REGALLOC-NEXT: $vgpr1 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
+ ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5)
+ ; REGALLOC-NEXT: $sgpr4 = V_READLANE_B32 $vgpr1, 2, implicit-def $sgpr4_sgpr5
+ ; REGALLOC-NEXT: $sgpr5 = V_READLANE_B32 $vgpr1, 3
+ ; REGALLOC-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
+ ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 5
+ ; REGALLOC-NEXT: renamable $vgpr0 = V_MUL_LO_U32_e64 killed $vgpr0, killed $sgpr4, implicit $exec
+ ; REGALLOC-NEXT: KILL killed renamable $vgpr1
+ ; REGALLOC-NEXT: SI_RETURN implicit killed $vgpr0
+bb.0:
+ %cmp = icmp slt i32 %arg0, 50
+ br i1 %cmp, label %bb.1, label %bb.2
+
+bb.1:
+ %val1 = add i32 %arg1, 10
+ br label %bb.3
+
+bb.2:
+ %val2 = add i32 %arg2, 20
+ br label %bb.3
+
+bb.3:
+ %val = phi i32 [ %val1, %bb.1 ], [ %val2, %bb.2 ]
+ %ret = mul i32 %val, 5;
+ ret i32 %ret
+}
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