[llvm] [AMDGPU] Add writelane and readlane pseudos for SGPR spilling (PR #69923)
Christudasan Devadasan via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 26 04:12:26 PDT 2023
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@@ -875,6 +875,28 @@ defm SI_SPILL_S384 : SI_SPILL_SGPR <SReg_384>;
defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
defm SI_SPILL_S1024 : SI_SPILL_SGPR <SReg_1024>;
+let SGPRSpill = 1, VALU = 1, isConvergent = 1 in {
+def SI_SPILL_S32_TO_VGPR : PseudoInstSI <(outs VGPR_32:$vdst),
+ (ins SReg_32:$src0, i32imm:$src1, VGPR_32:$vdst_in)> {
+ let Size = 4;
+ let FixedSize = 1;
+ let hasSideEffects = 0;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let Constraints = "$vdst = $vdst_in";
+}
+
+def SI_RESTORE_S32_FROM_VGPR : PseudoInstSI <(outs SReg_32:$sdst),
+ (ins VGPR_32:$src0, i32imm:$src1)> {
+ let Size = 4;
+ let FixedSize = 1;
+ let IsNeverUniform = 1;
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cdevadas wrote:
Ah. Thanks for spotting it. I was supposed to add it to the SI_SPILL_S32_TO_VGPR instruction. Will update it.
https://github.com/llvm/llvm-project/pull/69923
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