[llvm] [AArch64] Sink vscale calls into loops for better isel (PR #70304)

[Paul Walker via llvm-commits]

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@@ -14623,12 +14636,29 @@ bool AArch64TargetLowering::shouldSinkOperands(
     }
   }
 
-  if (!I->getType()->isVectorTy())
-    return false;
-
   switch (I->getOpcode()) {
   case Instruction::Sub:
   case Instruction::Add: {
+    // If the subtarget wants to make use of sve inc* instructions, then sink
+    // vscale intrinsic (along with any shifts or multiplies) so that the
+    // appropriate folds can be made.
+    if (Subtarget->useScalarIncVL()) {
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paulwalker-arm wrote:

Is this check necessary? I'm hopefully there are reasons[1] to lower the constant regardless of whether we'll ultimately emit inc/dec instructions.  Even if that does not happen MachineLICM should hoist the `rdvl` anyway.

For example, if the add/sub is then splatted we can use the vector variants regardless of `useScalarIncVL`.

https://github.com/llvm/llvm-project/pull/70304