[llvm] [AArch64] Sink vscale calls into loops for better isel (PR #70304)

[Paul Walker via llvm-commits]

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@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
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paulwalker-arm wrote:

Do we need code generation tests for an IR transformation? We already have tests that show inc/dec construction.

https://github.com/llvm/llvm-project/pull/70304