[llvm] [DAG] SimplifyDemandedBits - ensure we demand the high bits for shl nsw/nuw ops (PR #70041)

[Nikita Popov via llvm-commits]

nikic wrote:

> We're actually very badly split in SimplifyDemandedBits - so if you have a preferred approach I'll see if I can make it more consistent:
> 
> SHL does the dropPoisonFlags approach, but only for variable shifts. I'll take your suggestion and see what happens by adding it for the constant shift as well instead of what I tried first. I'm worried that promotions and address math might be relying on NUW/NSW in some places.
> 
> SRA/SRL adds extra demanded bits for EXACT and doesn't alter flags at all.

Looking closer, the situation in InstCombine seems to be quite similar to DAGCombine, with different approaches used for different instructions. I've submitted https://github.com/llvm/llvm-project/pull/70311 to switch to dropping the flag for `exact` shifts.

https://github.com/llvm/llvm-project/pull/70041