[llvm] [RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (PR #69788)

[Luke Lau via llvm-commits]

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@@ -1101,21 +1101,20 @@ define void @urem_v2i64(ptr %x, ptr %y) {
 define void @mulhu_v16i8(ptr %x) {
 ; CHECK-LABEL: mulhu_v16i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
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lukel97 wrote:

Yeah this test changed surprised me, it seems to be taking advantage of this existing bit of logic in the backward pass:
https://github.com/llvm/llvm-project/blob/46028022407d003b8af4ddf27a4679de4891f10d/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp#L372-L381

https://github.com/llvm/llvm-project/pull/69788