[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)

[Wang Pengcheng via llvm-commits]

================
@@ -27,29 +111,18 @@ static bool isLUIADDI(const MachineInstr *FirstMI,
   if (SecondMI.getOpcode() != RISCV::ADDI &&
       SecondMI.getOpcode() != RISCV::ADDIW)
     return false;
-
   // Assume the 1st instr to be a wildcard if it is unspecified.
   if (!FirstMI)
     return true;
 
   if (FirstMI->getOpcode() != RISCV::LUI)
     return false;
 
-  Register FirstDest = FirstMI->getOperand(0).getReg();
-
-  // Destination of LUI should be the ADDI(W) source register.
-  if (SecondMI.getOperand(1).getReg() != FirstDest)
+  // The first operand of ADDI might be a frame index.
----------------
wangpc-pp wrote:

> But now I am starting to wonder: can we guarantee that an edge always implies data dependency? What if some other mutation creates an artificial edge without data dependency for example?

Yes, I have to say that it's possible to have other order dependencies like `Artificial`. For example, `BaseMemOpClusterMutation::clusterNeighboringMemOps`. Though we may not add artificial edges (not for fusion) between ALU instructions. I haven't run into any problem after remove the `isReg()` yet, but I think we may add it back since there are some potential risks of assertion theoretically.


https://github.com/llvm/llvm-project/pull/70012