[llvm] [X86][NFC] Reorder the registers to reduce unnecessary iterations (PR #70222)

[Shengchen Kan via llvm-commits]

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@@ -616,6 +616,32 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   return Reserved;
 }
 
+unsigned X86RegisterInfo::getNumSupportedRegs(const MachineFunction &MF) const {
+  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
+  // All existing Intel CPUs that support AMX support AVX512 and all existing
+  // Intel CPUs that support APX support AMX. AVX512 implies AVX.
+  //
+  // We enumerate the registers in X86GenRegisterInfo.inc in this order:
+  //
+  // Registers before AVX512,
+  // AVX512 registers (X/YMM16-31, ZMM0-31, K registers)
+  // AMX registers (TMM)
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KanRobert wrote:

We can also see the difference by the update in llvm/test/CodeGen/X86/ipra-reg-usage.ll

https://github.com/llvm/llvm-project/pull/70222