[llvm] [RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (PR #70266)

[Michael Maitland via llvm-commits]

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@@ -62,6 +62,45 @@ multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
     def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
 }
 
+// Define a SchedAlias for the SchedWrite associated with (name, mx) whose
+// behavior is aliased to a Variant. The Variant has Latency predLad and
+// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has
+// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite
+// is created similiarly if IsWorstCase is true. The prefix is used to uniquely
+// define SchedWriteRes and Variant resources.
+multiclass LMULWriteResMXVariant<string name, SchedPredicate Pred,
+                                 list<ProcResourceKind> resources,
+                                 int predLat, list<int> predCycles,
+                                 int noPredLat, list<int> noPredCycles,
+                                 string mx, bit IsWorstCase, string prefix> {
+  defvar nameMX = prefix # name # "_" # mx;
+
+  // Define the different behaviors
+  def nameMX # "_Pred" : SchedWriteRes<resources>
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michaelmaitland wrote:

I am all ears if anyone has an idea to remove the use of `prefix`. The problem is that if we removed it and there is another processor who wants to create a LMULWriteResMXVariant for the same `name` and `mx`, then we will be creating two records with the same name, which is not allowed.

But using it feels awkward because we would like it to be in the namespace of the caller of LMULWriteResMXVariant. We cant give a name like `defm "SiFive7" : LMULWriteResMXVariant` because then it will suffix the SchedAlias with that, and we don't want that.

I tried to use `defvar Pred = SchedWriteRes<resources>;` but that leads to `error: Record `anonymous_53386', field `SchedModel' does not have a def initializer!`

https://github.com/llvm/llvm-project/pull/70266