[llvm] [RISCV] Macro-fusion support for veyron-v1 CPU. (PR #70012)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 25 12:51:31 PDT 2023
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@@ -954,6 +964,14 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
[TuneNoDefaultUnroll,
TuneShortForwardBranchOpt]>;
+def TuneVeyronFusions : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
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preames wrote:
Please separate this out in a separate PR which only adds the proc family and the existing LUI/ADDI fusion. Then this change can extend the list with the new fusions.
https://github.com/llvm/llvm-project/pull/70012
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