[llvm] [AMDGPU] Accept arbitrary sized sources in CalculateByteProvider (PR #70240)
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Wed Oct 25 11:50:10 PDT 2023
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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git-clang-format --diff 94aaaf4fb49c7057a9060a3d7888bdfb0c40734d 7bb3c9f1f702963d4f1dab83ed76905781d7ca62 -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index fd0ffe47b440..b64dd01b689f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10928,7 +10928,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
bool IsVec = Op.getValueType().isVector();
switch (Op.getOpcode()) {
case ISD::OR: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
auto RHS = calculateByteProvider(Op.getOperand(1), Index, Depth + 1,
StartingIndex, IsSigned);
if (!RHS)
@@ -10949,7 +10950,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
}
case ISD::AND: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
auto BitMaskOp = dyn_cast<ConstantSDNode>(Op->getOperand(1));
if (!BitMaskOp)
return std::nullopt;
@@ -10970,7 +10972,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
}
case ISD::FSHR: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(2));
if (!ShiftOp || Op.getValueType().isVector())
@@ -10996,7 +10999,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
case ISD::SRA:
case ISD::SRL: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1));
if (!ShiftOp)
return std::nullopt;
@@ -11022,7 +11026,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
}
case ISD::SHL: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1));
if (!ShiftOp)
return std::nullopt;
@@ -11047,7 +11052,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
case ISD::SIGN_EXTEND_INREG:
case ISD::AssertZext:
case ISD::AssertSext: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
SDValue NarrowOp = Op->getOperand(0);
unsigned NarrowBitWidth = NarrowOp.getValueSizeInBits();
if (Op->getOpcode() == ISD::SIGN_EXTEND_INREG ||
@@ -11078,7 +11084,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
}
case ISD::TRUNCATE: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
uint64_t NarrowByteWidth = BitWidth / 8;
if (NarrowByteWidth >= Index) {
@@ -11126,7 +11133,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
}
case ISD::BSWAP: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
return calculateByteProvider(Op->getOperand(0), BitWidth / 8 - Index - 1,
Depth + 1, StartingIndex, IsSigned);
}
@@ -11146,7 +11154,8 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
}
case AMDGPUISD::PERM: {
- if (IsVec) return std::nullopt;
+ if (IsVec)
+ return std::nullopt;
auto PermMask = dyn_cast<ConstantSDNode>(Op->getOperand(2));
if (!PermMask)
return std::nullopt;
@@ -11308,7 +11317,7 @@ static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
// TODO support constantZero
if (!P || P->isConstantZero())
return SDValue();
-
+
PermNodes.push_back(*P);
}
if (PermNodes.size() != 4)
``````````
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https://github.com/llvm/llvm-project/pull/70240
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