[llvm] [AMDGPU] New ttracedata intrinsics (PR #70235)
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Wed Oct 25 10:55:44 PDT 2023
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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git-clang-format --diff 0e4264ab1e7a3d82a32d0d096d014afade1e2fae e02640686a8cf0a42cec01da4f32b6888f5de11f -- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index f117f732cb84..ec4f3f1a1591 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4658,8 +4658,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
case Intrinsic::amdgcn_s_ttracedata: {
// This must be an SGPR, but accept a VGPR.
- unsigned Bank = getRegBankID(MI.getOperand(1).getReg(), MRI,
- AMDGPU::SGPRRegBankID);
+ unsigned Bank =
+ getRegBankID(MI.getOperand(1).getReg(), MRI, AMDGPU::SGPRRegBankID);
OpdsMapping[1] = AMDGPU::getValueMapping(Bank, 32);
break;
}
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https://github.com/llvm/llvm-project/pull/70235
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