[llvm] 8efd679 - [RISCV][GISel] Add clampScalar G_ZEXTLOAD/G_SEXTLOAD legalization rules.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 25 10:25:34 PDT 2023
Author: Craig Topper
Date: 2023-10-25T10:23:55-07:00
New Revision: 8efd6799f006000a5e3aacbb403f262db37290b6
URL: https://github.com/llvm/llvm-project/commit/8efd6799f006000a5e3aacbb403f262db37290b6
DIFF: https://github.com/llvm/llvm-project/commit/8efd6799f006000a5e3aacbb403f262db37290b6.diff
LOG: [RISCV][GISel] Add clampScalar G_ZEXTLOAD/G_SEXTLOAD legalization rules.
This fixes i8->i16 on RV32/RV64 and i8/i16/i32->i64 on RV64.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index d3e4b81c5cdb10b..b71207891fe1fca 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -119,7 +119,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
{XLenLLT, p0, s16, 16}});
if (XLen == 64)
ExtLoadActions.legalForTypesWithMemDesc({{XLenLLT, p0, s32, 32}});
- ExtLoadActions.lower();
+ ExtLoadActions
+ .clampScalar(0, s32, XLenLLT)
+ .lower();
getActionDefinitionsBuilder(G_PTR_ADD)
.legalFor({{p0, XLenLLT}});
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
index a473894e7bdc52b..a36ed5345790b9b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
@@ -2,6 +2,26 @@
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
+---
+name: zextload_i8_i16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i8_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s32) = G_ANYEXT %2(s16)
+ $x10 = COPY %3(s32)
+ PseudoRET implicit $x10
+
+...
---
name: zextload_i8_i32
body: |
@@ -39,6 +59,95 @@ body: |
$x10 = COPY %2(s32)
PseudoRET implicit $x10
+...
+---
+name: zextload_i8_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i8_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: zextload_i16_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i16_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: zextload_i32_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i32_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: sextload_i8_i16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s32) = G_ANYEXT %2(s16)
+ $x10 = COPY %3(s32)
+ PseudoRET implicit $x10
+
...
---
name: sextload_i8_i32
@@ -78,3 +187,75 @@ body: |
PseudoRET implicit $x10
...
+---
+name: sextload_i8_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: sextload_i16_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i16_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: sextload_i32_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i32_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $x10 = COPY %3(s32)
+ $x11 = COPY %4(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
index c24db2c38f7062e..9250c099cf0269a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
@@ -2,6 +2,27 @@
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
+---
+name: zextload_i8_i16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i8_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s64) = G_ANYEXT %2(s16)
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+
+...
---
name: zextload_i8_i32
body: |
@@ -100,6 +121,27 @@ body: |
$x10 = COPY %2(s64)
PseudoRET implicit $x10
+...
+---
+name: sextload_i8_i16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s64) = G_ANYEXT %2(s16)
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+
...
---
name: sextload_i8_i32
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