[llvm] [X86][NFC] Reorder the registers to reduce unnecessary iterations (PR #70222)

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git-clang-format --diff c9c9bf0f20fd820b86fac35113bbd8049ff4e72a 3da6138d51b6642e3ddd598f4e17d31adc3ce1e8 -- llvm/include/llvm/CodeGen/LiveVariables.h llvm/include/llvm/CodeGen/TargetRegisterInfo.h llvm/include/llvm/TableGen/Record.h llvm/lib/CodeGen/LiveVariables.cpp llvm/lib/Target/X86/AsmParser/X86Operand.h llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp llvm/lib/Target/X86/X86RegisterInfo.cpp llvm/lib/Target/X86/X86RegisterInfo.h llvm/utils/TableGen/CodeGenRegisters.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/include/llvm/CodeGen/LiveVariables.h b/llvm/include/llvm/CodeGen/LiveVariables.h
index 0c3414531ab1..5d7f9ff3053c 100644
--- a/llvm/include/llvm/CodeGen/LiveVariables.h
+++ b/llvm/include/llvm/CodeGen/LiveVariables.h
@@ -147,7 +147,7 @@ private:   // Intermediate data structures
   bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
 
   /// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
-  void HandleRegMask(const MachineOperand&, unsigned);
+  void HandleRegMask(const MachineOperand &, unsigned);
 
   void HandlePhysRegUse(Register Reg, MachineInstr &MI);
   void HandlePhysRegDef(Register Reg, MachineInstr *MI,
@@ -170,7 +170,8 @@ private:   // Intermediate data structures
   /// is coming from.
   void analyzePHINodes(const MachineFunction& Fn);
 
-  void runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs, unsigned NumRegs);
+  void runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs,
+                  unsigned NumRegs);
 
   void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
 public:
diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h
index ba0d0de79851..4ed727b40be9 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -1871,9 +1871,7 @@ public:
     return TrackedRecords;
   }
 
-  bool isAnonymous() const {
-    return IsAnonymous;
-  }
+  bool isAnonymous() const { return IsAnonymous; }
 
   void dump() const;
 
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 28a134cff9be..d0c44093de17 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -605,7 +605,8 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   }
   if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
     for (unsigned n = 0; n != 16; ++n) {
-      for (MCRegAliasIterator AI(X86::XMM16 + n, this, true); AI.isValid(); ++AI)
+      for (MCRegAliasIterator AI(X86::XMM16 + n, this, true); AI.isValid();
+           ++AI)
         Reserved.set(*AI);
     }
   }
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index b5162dda544f..5d7daa35bb1b 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -1176,9 +1176,9 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
     Idx.updateComponents(*this);
 
   // Read in the register and register tuple definitions.
-  std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
-  std::vector<Record*> Tups =
-    Records.getAllDerivedDefinitions("RegisterTuples");
+  std::vector<Record *> Regs = Records.getAllDerivedDefinitions("Register");
+  std::vector<Record *> Tups =
+      Records.getAllDerivedDefinitions("RegisterTuples");
   for (Record *R : Tups) {
     // Expand tuples and merge the vectors
     std::vector<Record *> TupRegs = *Sets.expand(R);

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https://github.com/llvm/llvm-project/pull/70222