[llvm] [AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (PR #68186)

[via llvm-commits]

================
@@ -1283,6 +1293,23 @@ bool AMDGPUCallLowering::lowerTailCall(
     MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
   }
 
+  // If this is a chain call, we need to set EXEC right before the call.
+  if (AMDGPU::isChainCC(Info.CallConv)) {
+    ArgInfo ExecArg = Info.OrigArgs[1];
+    assert(ExecArg.Regs.size() == 1 && "Too many regs for EXEC");
+
+    if (!ExecArg.Ty->isIntegerTy(ST.getWavefrontSize()))
+      return false;
+
+    unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
+    MCRegister Exec = TRI->getExec();
+    auto SetExec =
+        MIRBuilder.buildInstr(MovOpc).addDef(Exec).addReg(ExecArg.Regs[0]);
----------------
ruiling wrote:

I am not familiar with `AMDGPUMCInstLower`, so I don't know whether it is more proper place. If nothing wrong with it, I think it should be ok. I noticed there is still a scheduler run after `PostRAPseudos`. So, it would be better to be later than that, then we don't need to add an implicit use of `EXEC` to the s_setpc, which is a little bit strange.

https://github.com/llvm/llvm-project/pull/68186