[llvm] 34af57c - [RISCV][GISel] Add G_SEXTLOAD to legalizer and regbank select. Add instruction selection tests.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 25 00:15:12 PDT 2023
Author: Craig Topper
Date: 2023-10-25T00:13:21-07:00
New Revision: 34af57c5c170f80e3ad0dfb469bf7fcc99c2e1af
URL: https://github.com/llvm/llvm-project/commit/34af57c5c170f80e3ad0dfb469bf7fcc99c2e1af
DIFF: https://github.com/llvm/llvm-project/commit/34af57c5c170f80e3ad0dfb469bf7fcc99c2e1af.diff
LOG: [RISCV][GISel] Add G_SEXTLOAD to legalizer and regbank select. Add instruction selection tests.
This updates our G_SEXTLOAD support to the same level as G_ZEXTLOAD.
Still missing some legalizer rules for both though.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 014e178142f2f6f..d3e4b81c5cdb10b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -111,14 +111,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
.clampScalar(0, s32, XLenLLT)
.lower();
- auto &ZExtLoadActions = getActionDefinitionsBuilder(G_ZEXTLOAD)
- .legalForTypesWithMemDesc({{s32, p0, s8, 8},
- {s32, p0, s16, 16},
- {XLenLLT, p0, s8, 8},
- {XLenLLT, p0, s16, 16}});
+ auto &ExtLoadActions =
+ getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
+ .legalForTypesWithMemDesc({{s32, p0, s8, 8},
+ {s32, p0, s16, 16},
+ {XLenLLT, p0, s8, 8},
+ {XLenLLT, p0, s16, 16}});
if (XLen == 64)
- ZExtLoadActions.legalForTypesWithMemDesc({{XLenLLT, p0, s32, 32}});
- ZExtLoadActions.lower();
+ ExtLoadActions.legalForTypesWithMemDesc({{XLenLLT, p0, s32, 32}});
+ ExtLoadActions.lower();
getActionDefinitionsBuilder(G_PTR_ADD)
.legalFor({{p0, XLenLLT}});
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 4ede55fc8c54f68..10695a8033a9a72 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -133,6 +133,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_LOAD:
+ case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_ZEXTLOAD:
case TargetOpcode::G_STORE:
break;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
index b54e70848c3f585..b3744bba37c743d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
@@ -110,6 +110,50 @@ body: |
$x10 = COPY %1(s32)
PseudoRET implicit $x10
+...
+---
+name: sextload_i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[LB]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: $x10 = COPY [[LH]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
...
---
name: load_p0
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
index 76654d59d9c42ea..50e72ebe6ee5b3a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
@@ -176,6 +176,72 @@ body: |
$x10 = COPY %1(s64)
PseudoRET implicit $x10
+...
+---
+name: sextload_i8_i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[LB]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i16_i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i16_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: $x10 = COPY [[LH]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i32_i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i32_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))
+ ; CHECK-NEXT: $x10 = COPY [[LW]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
...
---
name: load_i8_i32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
new file mode 100644
index 000000000000000..a473894e7bdc52b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-extload.mir
@@ -0,0 +1,80 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: zextload_i8_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i8_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: zextload_i16_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i16_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i8_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i16_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i16_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
new file mode 100644
index 000000000000000..c24db2c38f7062e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-extload.mir
@@ -0,0 +1,202 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: zextload_i8_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i8_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s64) = G_ANYEXT %2(s32)
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: zextload_i16_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i16_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ %3:_(s64) = G_ANYEXT %2(s32)
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: zextload_i8_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i8_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: zextload_i16_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i16_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: zextload_i32_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: zextload_i32_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i8_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
+ %3:_(s64) = G_ANYEXT %2(s32)
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i16_i32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i16_i32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
+ %3:_(s64) = G_ANYEXT %2(s32)
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i8_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i8_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i16_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i16_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i32_i64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: sextload_i32_i64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
index ed86fb2725c7a01..81e8a5a6c8303f4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
@@ -129,3 +129,45 @@ body: |
PseudoRET implicit $x10
...
+---
+name: sextload_i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; RV32I-LABEL: name: sextload_i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
+ ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; RV32I-LABEL: name: sextload_i16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
index 64533de67d3b695..357c1895b158e2d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
@@ -114,6 +114,7 @@ body: |
PseudoRET implicit $x10
...
+---
name: zextload_i8
legalized: true
tracksRegLiveness: true
@@ -172,3 +173,62 @@ body: |
PseudoRET implicit $x10
...
+---
+name: sextload_i8
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ %0:_(p0) = COPY $x10
+ %3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
+ %2:_(s64) = G_ANYEXT %3(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; RV64I-LABEL: name: sextload_i16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
+ ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[SEXTLOAD]](s32)
+ ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
+ %2:_(s64) = G_ANYEXT %3(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sextload_i32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; RV64I-LABEL: name: sextload_i32
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32))
+ ; RV64I-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
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