[llvm] [AMDGPU] Add writelane and readlane pseudos for SGPR spilling (PR #69923)

[Carl Ritson via llvm-commits]

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@@ -875,6 +875,25 @@ defm SI_SPILL_S384 : SI_SPILL_SGPR <SReg_384>;
 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
 defm SI_SPILL_S1024 : SI_SPILL_SGPR <SReg_1024>;
 
+let SGPRSpill = 1 in {
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perlfu wrote:

Do we need to be marking these as isConvergent to match existing behaviour?
I think the answer is probably no as they have much narrower scope that v_readlane/v_writelane, but are still cross-lane operations. 

https://github.com/llvm/llvm-project/pull/69923