[llvm] [AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (PR #68186)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 24 18:17:43 PDT 2023
================
@@ -1283,6 +1293,23 @@ bool AMDGPUCallLowering::lowerTailCall(
MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
}
+ // If this is a chain call, we need to set EXEC right before the call.
+ if (AMDGPU::isChainCC(Info.CallConv)) {
+ ArgInfo ExecArg = Info.OrigArgs[1];
+ assert(ExecArg.Regs.size() == 1 && "Too many regs for EXEC");
+
+ if (!ExecArg.Ty->isIntegerTy(ST.getWavefrontSize()))
+ return false;
+
+ unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
+ MCRegister Exec = TRI->getExec();
+ auto SetExec =
+ MIRBuilder.buildInstr(MovOpc).addDef(Exec).addReg(ExecArg.Regs[0]);
----------------
ruiling wrote:
I think it would be more robust if we view it as kind of one pseudo instruction like `vector_call PC, mask` which got expanded later (maybe at `SILateBranchLowering`?). Can you see other possible issue with doing that?
https://github.com/llvm/llvm-project/pull/68186
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