[llvm] [RISCV] Remove RISCVISD opcodes for LGA, LA_TLS_IE, and LA_TLS_GD. (PR #70137)

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git-clang-format --diff 567a660a252323f2e82abaf48752dcad26d4779e 029dde4d9aa2a01458961bd6e0f5e7ee29ca383a -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index c262192c6..aab3169b9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -122,7 +122,8 @@ enum NodeType : unsigned {
   FPCLASS,
 
   // Floating point fmax and fmin matching the RISC-V instruction semantics.
-  FMAX, FMIN,
+  FMAX,
+  FMIN,
 
   // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
   // (returns (Lo, Hi)). It takes a chain operand.
@@ -135,10 +136,17 @@ enum NodeType : unsigned {
   UNZIP,
 
   // Scalar cryptography
-  CLMUL, CLMULH, CLMULR,
-  SHA256SIG0, SHA256SIG1, SHA256SUM0, SHA256SUM1,
-  SM4KS, SM4ED,
-  SM3P0, SM3P1,
+  CLMUL,
+  CLMULH,
+  CLMULR,
+  SHA256SIG0,
+  SHA256SIG1,
+  SHA256SUM0,
+  SHA256SUM1,
+  SM4KS,
+  SM4ED,
+  SM3P0,
+  SM3P1,
 
   // Vector Extension
   FIRST_VL_VECTOR_OP,

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https://github.com/llvm/llvm-project/pull/70137